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[03:49:15] <skunksleep> zlog
[03:49:16] <zlog> skunksleep: Log stored at
http://tom-itx.no-ip.biz:81/~tom-itx/irc/logs/%23linuxcnc-devel/2015-05-12.html
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[13:09:18] <jepler> https://lwn.net/Articles/643918/ Jailhouse 0.5 released ... Linux-based partitioning hypervisor Jailhouse ... Consequently, running cyclictest over a -rt kernel in a cell gives native latencies
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[13:50:06] <seb_kuzminsky> jepler: neat!
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[15:27:34] <cradek> aha!
[15:27:36] <cradek> [ 103.793630] Failed to communicate with pluto-servo board after programming firmware.
[15:28:01] <cradek> the error message is the same, but after adding 220 pullup to +5 on strobe, it programs (the LED goes out)
[15:29:40] <cradek> I wonder if I need pullups on some other pins too
[15:32:00] <cradek> maybe 14, 17
[15:34:30] <pcw_home> also, is it really getting set into EPP mode?
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[15:36:48] <pcw_home> I think that the open drain outputs (at least on some parallel port hardware) change to push-pull when in EPP mode
[15:42:08] <kwallace> I would think the Pluto would need EPP to do any (two-way) communication with the parallel port?
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[15:55:39] <cradek> pin 16 needs pullup, 14 seems sharp, I only see one low pulse, maybe after programming? it's 70ns wide
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[15:57:00] <cradek> ahh 17 is slow rise too
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[15:58:01] <cradek> I'm going to add pullups to 14,16,17
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[16:04:36] <pcw_home> My experience with the Sun1888 with a 7I43 (years ago) was that it would not work with a long cable, maybe its the same issue
[16:04:50] <cradek> interesting
[16:17:11] <cradek> those three pullups made the signals look nice, but it still fails to communicate after (successful) programming
[16:19:52] <pcw_home> maybe its not in EPP mode
[16:20:40] <cradek> you mean the sun card?
[16:21:20] <jepler> outb(0x80, ioaddr_hi + 0x2); // select EPP mode in ECR
[16:21:27] <jepler> this is what pluto driver does to switch from SPP to EPP mode
[16:21:59] <jepler> if(board[i].port.base_hi) {
[16:21:59] <jepler> outb(0x94, board[i].port.base_hi + HM2_7I43_ECP_CONTROL_HIGH_OFFSET); // select EPP mode in ECR
[16:22:03] <jepler> vs what 7i43 does
[16:22:20] <jepler> hm2_7i43_epp_write_control(0x04, &board[i]); // set control lines and input mode
[16:22:33] <jepler> 7i43 also does this
[16:24:11] <jepler> bit 4 is "ecp interrupt bit", bit 3 is "dma enable bit". It's surprising to me to set those bits true for EPP mode.
[16:24:28] <jepler> (bits 4 and 3 of ECP ECR, the difference between 0x80 and 0x94)
[16:26:14] <jepler> cradek: have you run a mesa epp board on this parport?
[16:27:49] <cradek> nope, interesting idea
[16:32:41] <pcw_home> I can't remember what I did to test the SUN1888
[16:32:43] <pcw_home> probably just set EPP mode by hand and ran my loopback test
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[17:09:59] <skunkworks> that should be part of the printer port driver... That would fix issues some have with the gecko 540
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[17:13:05] <skunkworks> seems setting the port to EPP in the bios doesn't alway make linux see it as EPP
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[17:16:33] <PCW> yeah there's some pretty weird PP hardware out there (and really none of it should require a driver)
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[17:48:59] <skunkworks> right.
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[19:04:19] <cradek> http://pastie.org/10187289
[19:04:46] <cradek> the 7i43 DONE light turns off, but it doesn't work
[19:05:35] <cradek> unfortunately I am 70% sure this 7i43 works (it's very old, from seb, with some rework on it)
[19:07:40] <PCW> Done light turning off is a good sign (programmed OK via EPP)
[19:08:10] <PCW> so valid bit file CRC etc
[19:08:30] <cradek> epp is used for programming it?
[19:08:38] <PCW> yes
[19:09:12] <cradek> I have so many unknowns...
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[19:09:51] <PCW> unless the driver emulates EPP by byte banging but I dont think so
[19:11:36] <PCW> CPLD handles EPP handshake until FPGA is programmed then hands control to FPGA (when DONE is asserted)
[19:12:49] <cradek> so you think this could be a bad 7i43?
[19:14:01] <PCW> possibly but if you got done to go out I think its not too likely
[19:14:31] <PCW> only power LED on when programmed?
[19:14:32] <archivist> using the same par port as earlier experiments you were talking about?
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[19:17:34] <PCW> at power up there should be three lights on
[19:17:35] <PCW> Yellow power
[19:17:37] <PCW> Red /INIT
[19:17:38] <PCW> Red /DONE
[19:17:40] <PCW> only yellow power LED should remain on after programming
[19:17:57] <cradek> init stays on after programming
[19:18:36] <cradek> yeah only DONE turns off
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[19:21:47] <PCW> hmm that could be a CRC error
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[19:22:39] <cradek> I picked at random config=firmware=hm2/7i43/SVST4_4B.BIT
[19:22:39] <PCW> I was not even aware that was possible (done asserted but bad FPGA load)
[19:23:11] <PCW> any should be fine
[19:23:45] <PCW> as long as it for a 7I43 with the correct size FPGA
[19:24:01] <PCW> 400K version?
[19:24:15] <cradek> [ 1569.366287] hm2/hm2_7i43.0: board has FPGA '3s400tq144', but the firmware in hm2/7i43-2/SVST4_4.BIT is for FPGA '3s200tq144'
[19:24:20] <cradek> oh another tells me this
[19:24:22] <cradek> lemme try a -4
[19:25:26] <cradek> 7i43-4/SVST4_4.BIT does the same thing - DONE led turns off
[19:25:47] <PCW> short cable?
[19:25:51] <cradek> with 7i43-2/SVST4_4.BIT both lights stay on, I get that "wrong size" error
[19:26:02] <cradek> yes 3' or less
[19:26:06] <cradek> let me try another
[19:26:16] <PCW> arghh
[19:27:43] <PCW> maybe cycle power since DONE asserted but bad FPGA load it not recoverable any other way
[19:28:05] <cradek> argh it's the wrong gender
[19:28:15] <cradek> I have cycled power (unplugged usb) each time
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[19:29:28] <cradek> haha
[19:29:35] <cradek> third cable, both LEDs turn off, computer hangs
[19:30:28] <cradek> first DONE turned off, then INIT also turned off
[19:30:34] <cradek> rebooting...
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[19:32:48] <cradek> yep same again, DONE turns off, INIT turns off, pc hangs
[19:32:54] <cradek> wt absolute f
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[19:34:06] <PCW> thats odd, /init should go out immediately when programming starts then /done should goe off when programming completes
[19:34:37] <micges> cradek: did you tried to use mesaflash to communicate with board?
[19:34:49] <cradek> nope
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[19:35:31] <cradek> this is all insane
[19:35:58] <cradek> rebooting again!
[19:36:08] <cradek> sure wonder what the crash is
[19:37:11] <PCW> EPP can hold the CPU (well ISA state machine) in a wait state but max time should be 10 usec
[19:37:43] <cradek> DONE definitely turns off first
[19:38:17] <cradek> last message on the console: hm2_7i43: loading HostMot2 Mesa 7i43 driver version 0.3
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[19:39:57] <cradek> ooh cable #4 has the right genders
[19:40:20] <cradek> some of these might be super duper old scsi cables
[19:42:05] <cradek> cable #4, both lights go out, machine does not hang, this error:
[19:42:06] <cradek> [ 110.547714] hm2/hm2_7i43.0: invalid cookie, got 0xFFFFFFFF, expected 0x55AACAFE
[19:42:09] <cradek> [ 110.547774] hm2/hm2_7i43.0: FPGA failed to initialize, or unexpected firmware?
[19:42:12] <cradek> [ 110.547828] hm2_7i43.0: board at (ioaddr=0xEC00, ioaddr_hi=0xE880, epp_wide ON) not found!
[19:42:34] <skunksleep> I can't believe you don't have zip drive cables :)
[19:42:57] <cradek> was that db25 scsi? some of these might be.
[19:43:02] <PCW> epp issues maybe, flat cables work well if short
[19:43:21] <cradek> there's a flat on the 7i43 but it's female so I can't plug it in directly
[19:44:46] <cradek> halcmd: loadrt hm2_7i43 config=firmware=hm2/7i43-4/SVST4_4.BIT ioaddr=0 epp_wide=0
[19:44:51] <cradek> this LOADED
[19:44:57] <cradek> epp_wide=0 is key
[19:45:52] <cradek> I can turn LEDS on
[19:45:55] <PCW> didnt someone suggest that for the Pluto as well?
[19:46:00] <cradek> yes
[19:46:13] <cradek> so now... known-good cable, known-good non-wide EPP comms
[19:46:36] <cradek> known-good 7i43
[19:46:38] <cradek> whee
[19:46:39] <PCW> well fewer variables...
[19:46:42] <cradek> a lot fewer
[19:46:59] <cradek> this cable is the one with my name carefully written on both ends
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[19:47:12] <cradek> some time in the past I've felt very possessive about it
[19:47:29] <PCW> jeeez, even Ethernet is easier
[19:47:49] <cradek> 5 s32 RO 227367 hm2_7i43.0.read.time
[19:47:49] <cradek> 5 s32 RW 269676 hm2_7i43.0.read.tmax
[19:47:58] <cradek> aren't those huuuuge times?
[19:48:04] <PCW> ping rarely crashes the computer
[19:48:28] <PCW> yes pretty big
[19:48:41] <cradek> 5 s32 RO 146772 hm2_7i43.0.write.time
[19:48:41] <cradek> 5 s32 RW 206082 hm2_7i43.0.write.tmax
[19:48:50] <PCW> unless you have a 10 GHz cpu
[19:48:54] <cradek> 5 s32 RO 18828 hm2_7i43.0.pet_watchdog.time
[19:48:54] <cradek> 5 s32 RW 31023 hm2_7i43.0.pet_watchdog.tmax
[19:48:57] <cradek> 1.8 GHz
[19:49:16] <cradek> ok, going to try pluto again
[19:50:13] <cradek> minor gender problems, no big deal
[19:51:39] <cradek> Failed to communicate with pluto-servo board after programming firmware.
[19:51:49] <cradek> nope nope
[19:51:51] <cradek> sigh
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[20:17:32] <jepler> cradek: did you put back the forever-missing double-read in pluto_clear_error_register?
[20:18:57] <cradek> yes
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[20:21:07] <cradek> I can't find any other important differences between the pluto and hm2 epp code
[20:22:24] <cradek> - outb(0x80, ioaddr_hi + 0x2); // select EPP mode in ECR
[20:22:24] <cradek> + outb(0x94, ioaddr_hi + 0x2); // select EPP mode in ECR
[20:22:30] <cradek> I tried this too
[20:23:40] <jepler> well that leaves us with there being a real problem in the pluto fpga firmware
[20:24:00] <cradek> or possibly still another hardware problem
[20:24:39] <cradek> on the pluto itself, I mean
[20:24:42] <jepler> tinkerer sent you an alternate firmware file, are your latest tests with it?
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[20:25:05] <cradek> I think he just sent me led-blink which was to test the programming
[20:25:20] <cradek> but I think the programming works fine, because of the led reliably going out now
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[20:39:55] <jepler> tinkerer's firmware added extra registers in the FPGA for the address and data strobes. his tarball from 2013 in private mail includes updated bitfiles (rbf). I put a copy here
http://emergent.unpythonic.net/files/sandbox/pluto_new.tgz
[20:40:37] <jepler> though unfortunately he seems only to have modified pluto_step_firmware
[20:41:09] <cradek> src/hal/drivers/pluto_servo_firmware/pluto_servo.rbf
[20:41:10] <cradek> src/hal/drivers/pluto_servo_firmware/pluto_servo_opendrain.rbf
[20:41:10] <cradek> src/hal/drivers/pluto_servo_firmware/pluto_servo_orig_broken.rbf
[20:41:10] <cradek> src/hal/drivers/pluto_servo_firmware/pluto_servo_rbf.working
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[20:42:36] <jepler> confusing. the -rwx------ 1 jepler jepler 19895 Oct 27 2013 pluto_stepper.rbf
[20:42:46] <jepler> I think this is the one you would want to try, to see if epp communication works
[20:43:05] <cradek> ok
[20:43:55] <jepler> this is also interesting
[20:43:55] <jepler> src/hal/drivers/pluto_servo_firmware/pluto_servo.rbf | Bin 19897 -> 19895 bytes
[20:44:04] <jepler> #define FIRMWARE_SIZE 19895
[20:44:22] <jepler> I wonder how important those last two bytes are
[20:47:02] <jepler> aka I wonder whether the fpga knows if it got a good bitstream
[20:49:12] <cradek> [ 4160.627254] Failed to communicate with pluto-servo board after programming firmware.
[20:49:29] <cradek> using pluto_servo.rbf from _new does not help this
[20:49:46] <jepler> try with pluto_stepper.rbf
[20:49:57] <jepler> bsaed on the diffs he only modified the stepper firmware
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[20:50:12] <jepler> and even then, put it under a different name
[20:50:16] <jepler> pluto_stepper.rbf, not pluto_step.rbf.
[20:51:30] <jepler> though he must have rebuilt pluto_servo, the evidence seems to indicate it probably does not have modifications to the EPP protocol handling
[20:51:37] <cradek> ok
[20:51:52] <cradek> I renamed his _stepper.rbf to _step.rbf and rebuilt
[20:51:54] <cradek> let's see
[20:53:05] <cradek> [ 4382.477245] Failed to communicate with pluto-servo board after programming firmware.
[20:53:08] <cradek> nope
[20:53:17] <cradek> (it must always say -servo in this error)
[20:53:24] <jepler> yes, apparently
[20:53:45] <jepler> so what you did was untar that thing, then copy just the one rbf file into your source tree in the right spot with the right name?
[20:53:51] <cradek> yes
[20:54:06] <jepler> and you reset the pluto etc
[20:54:07] <cradek> and I saw the build ran rbf2h
[20:54:15] <cradek> I'm going to power off for good measure
[20:57:25] <cradek> Failed to communicate with pluto-servo board after programming firmware.
[20:59:48] <jepler> sigh
[20:59:55] <cradek> fixing the SIZE define doesn't help
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[21:03:08] <jepler> I don't seem to have an e-mail that really explains what the change is about. I wonder if there was discussion on irc or something
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[21:03:15] <jepler> oblique references to an "open collector problem"
[21:03:18] <jepler> in my mail
[21:03:38] <jepler> which .. seems relevant to what has been going on with you
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[22:28:34] <andypugh> I just noticed that the INI-config documentation does not mention the [PYTHON] section referred to here:
http://www.linuxcnc.org/docs/html/remap/structure.html#_upgrading_an_existing_configuration_for_remapping
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