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[03:00:38] <jepler> http://www.clifford.at/icestorm/ "Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files." "We have enough bits mapped that we can create a functional verilog model for almost all bitstreams generated by Lattice iCEcube2 for the iCE40 HX1K-TQ144, as long as no block memories or PLLs are used. (Block memor
[03:00:44] <jepler> ies are fully documented, but the icebox_vlog.py script does not create verilog models for them yet.)"
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[03:28:26] <pcw_home> The ICE40 chips are nice for small things and quite inexpensive
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[03:32:31] <pcw_home> they are a bit like cheaper faster Spartan2s (4LUTs no multipliers)
[03:32:33] <pcw_home> so rather "Spartan" but have built in OTP Flash for low cost high volume apps
[03:32:50] <pcw_home> (you can use external SPI also)
[03:35:22] <Tom_itx> pcw_home rigid tapping / motion sync appears to be working now. not sure what the scale issue was about. thanks for the help
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[11:18:37] <jepler> http://www.iro.umontreal.ca/~feeley/papers/BergeronFeeleyDavidNEWCAS07.pdf
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