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[00:15:27] <KGB-linuxcnc> 03Dewey Garrett 05dgarr/halcheck 24725c5 06linuxcnc 10docs/src/config/ini_config.txt 10lib/hallib/README 03lib/hallib/halcheck.tcl 10tcl/twopass.tcl halcheck: library halfile to check common errors * 14http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=24725c5
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[00:55:22] <mozmck> I notice that in a python program, there is a hal-pin-changed signal - can something like this be done in C as well?
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[01:37:30] <KGB-linuxcnc> 03Dewey Garrett 052.7 a8bef41 06linuxcnc 10docs/src/config/ini_config.txt 10lib/hallib/README 03lib/hallib/halcheck.tcl 10tcl/twopass.tcl halcheck: library halfile to check common errors * 14http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=a8bef41
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[01:38:24] <KGB-linuxcnc> 05dgarr/halcheck 24725c5 06linuxcnc 04. branch deleted * 14http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=24725c5
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[04:37:59] <KGB-linuxcnc> 03Dewey Garrett 052.7 bad7066 06linuxcnc 10docs/src/config/ini_config.txt 10lib/hallib/halcheck.tcl halcheck: suppress gui if no errors * 14http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=bad7066
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[06:14:02] <cmorley> mozmck: I would think if you initialized hal_glib.py from a c program you could. Or write a c equivalent. but it is not bin done AFAIK.
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[14:08:55] <cradek> > I have gang tooling can you add support for it ... why not use tool offsets ... oh I didn't know about those thanks
[14:08:58] <cradek> :-)
[14:09:02] <cradek> some threads go fast
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[15:47:34] <seb_kuzminsky> every once in a while a user goes away happy, that's nice :-)
[15:52:18] <skunkworks> I don't believe it... ;)
[15:53:51] <skunkworks> other than gene saying that the docs suck on explaining it.. ;)
[15:54:14] <seb_kuzminsky> well...
[15:55:00] <cradek> gene has never met a documentation he likes
[15:56:30] <cradek> although it does talk exclusively about "length" which is kind of out of date
[15:57:27] <skunkworks> I guess I never looked at the docs.. just the tool table.
[15:59:11] <archivist> there are tool types not covered in the current table
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[16:22:34] <seb_kuzminsky> cradek: when i pushed just now i got this error:
[16:22:34] <seb_kuzminsky> remote: Transport error: 500 Can't connect to localhost:9999 (Invalid argument)
[16:22:38] <seb_kuzminsky> remote: Unable to relay message. All servers failed
[16:22:46] <seb_kuzminsky> the push went through, but kgb didn't announce it
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[16:25:24] <seb_kuzminsky> the email went out
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[16:49:24] <cradek> > I had a problem posting to event Got_Request of session SOAPServer for DIR handler '.*'
[16:49:43] <cradek> kgb reports this error in some language I don't speak
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[16:50:48] * cradek kicks KGB-linuxcnc in the SOAPServer
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[17:08:38] <Roguish> pcw_home: hey, I got the fpga changed on a 5i20. everything shows ok in lspci and mesaflash. but get an error 'invalid cookie, is xxxx, should be yyyy' when loading hm2. what's up?
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[17:10:28] <kwallace> Has anyone had trouble with gtksourceview and a line "<!-- interface-requires gtksourceview 0.0 -->" in the Glade file? With my setup with libgtksourceview2.0, when I open a glade file, Glade weeds out the requires comment and removes the sourceview widget. When I save the file, these bit are now missing and running the application barfs. I changed the requires to 2.0 and now Glade is happy and the sourceview survives. I'm just wondering where
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[17:12:23] <pcw_home> Roguish: hmm, probably an open or short (the xxxx and yyyy are good hints where if you have a schematic)
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[17:14:01] <Roguish> ok, i have the actual error message. how do i decode the xxxx and yyyy? do you mean schematic of the board? it errors with no cables attached.
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[17:27:14] <pcw_home> I can look at the schematic of you have the xxxx (but if xxxx is 0x00000100 or 0xFFFFFFFF its will be tougher)
[17:27:58] <pcw_home> i would look under a microscope at the FPGA soldering
[17:31:04] <Roguish> ok. 0x558ACAFE expected 0x55AACAFE
[17:31:43] <pcw_home> OK a single bit error
[17:32:44] <Roguish> yeah, i have some microscope work to do on my other 5i20. it does not boot yet and i can see a couple of buggers on the fpga leads. so i will be back at my friend's shop down off Regatta blvd to use his miroscope and metcal.
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[17:32:56] <pcw_home> bit 21 open probably
[17:33:26] <pcw_home> pretty sure this is on the bottom edge of the FPGA
[17:36:25] <Roguish> how do you determine it's bit 21? in case it changes as I work on the board..... I would like to be able to track the problem.
[17:37:16] <pcw_home> 0x558ACAFE xor 0x55AACAFE = 0x00200000
[17:37:43] <kwallace> Ah ha, Glade inserts the requires 0.0 line when a sourceview widget is added to the file from the pallet.
[17:38:46] <pcw_home> = 0b00000000001000000000000000000000
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[17:40:37] <Roguish> and how does that map to the fpga?
[17:43:15] <pcw_home> you need the schematic to get the FPGA pins, let me see if theres a copy online
[17:44:51] <pcw_home> freeby.mesanet.com/5i20sch.zip
[17:50:36] <Roguish> got it. looking at schematic. how do I find the correct pin?
[17:52:45] <pcw_home> look at the FPGA page and find data bit 21
[17:53:05] <pcw_home> not sure what its named but it ends in 21
[17:53:39] <pcw_home> maybe LAD21
[17:56:55] <Roguish> yes, there is an LAD21. goes to pin 149. are the pins numbered around cw or ccw on the fpga?
[17:57:59] <Roguish> the fpga is on the board with pin 1 in the upper right corner looking at the board with the pci fingers on the bottom.
[17:59:03] <pcw_home> google ds001.pdf
[17:59:55] <Roguish> spartan ii datasheet, dated jume 13, 2008
[18:00:30] <pcw_home> oops may that one doesn't have the pictures
[18:06:21] <Roguish> found a pinout table.
[18:14:20] <Roguish> ok, found an image of the PQ208 packag.
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[18:42:51] <Roguish> pcw_home: could it be IO21, not LAD21 ? or LAD22? the 1` is in position 22 of the binary number.
[18:43:22] <pcw_home> IO is GPIO so not the issue
[18:44:05] <pcw_home> 22nd position is bit 21
[18:44:15] <pcw_home> (bits start at 0)
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[18:57:22] <Roguish> pcw_home: ok. got my sharpest probes, best magnifying glass and a bright light, and it seems the pin 149 is open.
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[18:59:26] <cradek> I'd look at the rest of them too...
[19:01:10] <Roguish> gonna try and put a finer point on the probes. really need a microscope !!!! damn getting old sucks.
[19:01:22] <cradek> better than not getting old
[19:01:50] <Roguish> yeah, that's the way i look at it too. not quite ready for the dirt nap.
[19:02:21] <cradek> <- has a good microscope
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[19:39:22] <Roguish> pcw_home: FIXED IT. loads properly. THANKS. gotta bet a microscope, finer probes, and finer iron tip.
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[19:54:25] <skunkworks> was it a short?
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[20:58:10] <skunkworks> Can you run glade as stand alone like pyvcp?
[20:58:36] <skunkworks> Gladevcp
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[21:43:18] <kwallace> skunkworks, I have a stand alone GladeVCP example here:
http://www.wallacecompany.com/machine_shop/LinuxCNC/gvcpDRO/
[21:44:08] <skunkworks> kwallace: thanks! that is what I am looking for.
[21:44:25] <kwallace> Cool.
[21:48:03] <cradek> sherline hasn't updated their install since 2011?
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[22:08:31] <skunkworks> ouch
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[22:23:13] <PCW> ~1 week at 4 KHz hm2_eth after I turned off _all_ fan controls (motherboard had 2 case fan controls in addition to CPU fan)
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[23:44:59] <seb_kuzminsky> i bet a lot of these magic bios settings for latency would just disappear with coreboot
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