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[01:46:49] <jepler> bounce bounce
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[02:49:49] <skunkworks_> so it seems rt_prempt runs more correctly on the k&t motherboards also.
[02:50:06] <skunkworks_> maxes out at about 70us
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[03:31:19] <pcw_home> When I add the DPLL sampling to the encoder, even a few 100 usec of jitter should be fine
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[03:34:52] <skunkworks_> pcw_home: very exciting!
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[04:19:56] <ve7it> jepler,cradek it looks like the linuxcnc dropbox is no longer.... the link
http://linuxcnc.org/dropbox/cxf_fonts.tgz gives a 404 (from the wiki pages) is this new?
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[13:24:00] <jepler> ve7it: I googled it for you and found
http://fennetic.net/irc/cxf_fonts.tgz
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[14:53:43] <jepler> hm, my assembler is having a problem with the ambiguity of parsing 'STA XYZ' when 'STA X' and 'STA *' are both patterns
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[15:08:39] <pcw_home> hmm sta x could be changed to stx (sty,stz,stt)
[15:08:40] <pcw_home> or all sta * could be changed to sta *,0 but thats a pain to type
[15:09:21] <pcw_home> or stax stay staz stat
[15:09:31] <jepler> yeah I did that latter thing
[15:09:54] <jepler> now I'm to the "stare at hex listings and guess why there are differences" stage
[15:11:37] <pcw_home> i had a disassembler and single stepper at one point...
[15:12:13] <jepler> what really helped me last time around was that I also had the annotated output of your assembler
[15:15:24] <pcw_home> which ROM are you building?
[15:15:29] <jepler> etherhm2
[15:16:01] <pcw_home> i shoud be able to get the lst file from here
[15:16:15] <jepler> and of course being really confident the .vhd and the .asm match helps. the first few differences are jump targets varying by a few insns (not off by a factor of 2) and then it goes completely off the rails
[15:17:00] <pcw_home> probably a version issue
[15:17:11] <jepler> it has happened before
[15:18:53] <jepler> you committed an etherhm2.vhd and etherhm2.zip to hostmot2-firmware on the same day, so I started there
[15:19:36] <pcw_home> freeby.mesanet.com/ETHERHM2.ZIP
[15:19:38] <pcw_home> freeby.mesanet.com/ETHERHM2.LST
[15:19:39] <pcw_home> should match
[15:19:45] <jepler> thanks
[15:20:53] <pcw_home> last change was adding the ICAP stuff (V15)
[15:21:39] <jepler> does that need other changes to the .vhd ?
[15:25:25] <pcw_home> yes the latest changes require new top level files and new module files
[15:25:25] <pcw_home> TopEthernet,TopSerial,TopGCSPI,TopEPPS,TopPCI all changed
[15:25:27] <pcw_home> added files, ubrategend.vhd,kubstepgenzd.vhd,kubstepgenzid.vhd,fixicap.vhd
[15:26:23] <jepler> dout jmpnz dhigh
[15:26:29] <jepler> oh and my assembler won't expand jmpnz as a macro here
[15:33:42] <pcw_home> well that was just a bug in TASM jmpnz should be native
[15:34:16] <pcw_home> but it computed the jump addresses *2
[15:34:21] <jepler> right
[15:36:10] <pcw_home> probably best to just remove the R-s in the table
[15:40:07] <jepler> yay, the difference was whether debugset.asm was included
[15:41:32] <pcw_home> pretty sure its beyond needing that :-)
[15:42:06] <jepler> etherhm2.lst has the debug stuff in there, even though it was commented out in etherhm2.asm
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[15:42:31] <pcw_home> thats strange
[15:44:45] <pcw_home> maybe the commentting-out failed with Tasm
[15:44:46] <pcw_home> ;.include "debugset.asm"
[15:46:01] <jepler> so what happens if I try to use this ROM with a pre-icap vhd framework, assuming I never invoke the icap functionality via mesaflash?
[15:46:53] <pcw_home> should be fine (and icap stuff will justbe a noop)
[15:47:35] <pcw_home> (its will read/write memory instead of ICAP register)
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[15:52:46] <pcw_home> need to get micges to add the --test option to mesaflash so you can try dangerous changes without as much risk
[15:54:55] <pcw_home> (this of course depends on ICAP working)
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[15:59:07] <jepler> that'd be nice
[16:00:33] <pcw_home> simplest thing would be write test config to fallback area at use ICAP to start FPGA load from fallback area
[16:01:03] <jepler> it sort of reverses the meaning of the main and fallback areas..
[16:01:30] <pcw_home> Yeah but if its bad, a power cycle will fix it
[16:02:47] <pcw_home> fancier option is to see if there's space in the flash for loading the test config without overwriting anything
[16:05:51] <jepler> I see 7i90 has just 3 reserved/unused/free but a configuration takes 6 blocks so that doesn't seem like it'll work
[16:07:04] <pcw_home> well you have a proto 7I90 with a 8M bit flash, to consolidate parts we have started using 16M most places
[16:08:04] <pcw_home> so all the slx9 parts should have space
[16:09:42] <pcw_home> smarter allocation than putting the main config 1/2 way up might help but not sure its worth the changeover trouble
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[16:19:36] <jepler> I think that mesaflash will rewrite the boot block anytime it is different than expected
[16:20:06] <jepler> so as long as you don't move fallback, but move the user configuration up to the lowest available block, I think it'll work transparently
[16:21:26] <jepler> mesaflash will just say BootBlock installed
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[16:28:50] <pcw_home> Yeah so I guess thats OK
[16:30:34] <pcw_home> still no room for 3 slx9 configs in 8M :-(
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[16:33:44] <micges-dev> mesaflash will overwrite boot block if it's 25,26th bytes doesn't point at 1/2 flash address
[16:34:25] <micges-dev> I think it should it should be possible to not check boot block while write/verify
[16:34:45] <pcw_home> I think when we started the serial EEPROMS were expensive enough the we chose the smallest that would allow 2 configs
[16:36:11] <micges-dev> --no-boot-check?
[16:37:10] <pcw_home> not sure why you would not check
[16:39:23] <jepler> mesaflash would also have to modify its calculation for where the user blocks start, it wouldn't be size/2 anymore
[16:40:00] <jepler> it would probably have to come from a table instead, but in general it would have to be <= 1/3 for the three configuration way to work (fallback, user, icap)
[16:40:40] <jepler> ah, it's for bitcoin mining. 4 Spartan 6 LX150s sounds like a lot of FPGA.
http://www.ztex.de/usb-fpga-1/usb-fpga-1.15y.e.html
[16:41:36] <pcw_home> as long as the boot block is always updated to match the last location of the user config everything should be fine
[16:42:14] <pcw_home> (verify would need to read the boot block to find out where the user config starts)
[16:43:22] <jepler> verify first checks the boot block and rejects it if it's not the same one it would write
[16:43:26] <jepler> currently
[16:43:50] <pcw_home> OK
[16:44:25] <pcw_home> 4x XC6SLX150s has got to be pretty expensive
[16:45:09] <jepler> on their shop page the price is $492. they've also got a board with one xc7a200t for $562
[16:45:40] <jepler> I did play with cryptocurrency for a few weeks but came to my senses
[16:46:33] <pcw_home> I thought most of the bitcoins stuff was done with ASICS nowdays
[16:46:50] <jepler> yes, I think that's true
[16:49:12] <jepler> I was playing with dogecoin, in which one of the design choices attempted to make it unsuitable for ASIC mining -- the hashing algorithm is scrypt, which was designed to need a fairly large RAM (~128kB?) with unpredictable access patterns
[16:49:38] <pcw_home> asics have a huge power and speed advantage for fixed tasks (if theres enough volume to cover the NRE)
[16:50:03] <jepler> there are a lot of people who are willing to buy bitcoin mining hardware
[16:51:07] <pcw_home> reminds me of the low latency stock trading stuff, all this tech for silly purposes
[16:51:13] <jepler> all in all, I "mined" somewhat less than $5 worth of dogecoin with somewhere around 1 CPU*year of effort, which it turns out is hard to exchange for USD anyway. and I think it's declined in value to under $2 now.
[16:53:46] <jepler> I admire the idea of cryptocurrency, and some things about the design of various currencies are pretty neat, but in practice it seems to be a bunch of speculators plus a few companies who make money selling them hardware
[16:55:07] <pcw_home> Yeah to me, the whole thing seem uncomfortably close to a pyramid shceme
[16:55:09] <pcw_home> for stock trading I like this idea:
[16:55:10] <pcw_home> http://en.wikipedia.org/wiki/IEX
[16:57:15] <jepler> I've read some of the reporting around "flash boys" and it is an interesting story
[16:59:36] <jepler> for my part, I'd love a system for POS and online sales that pushes fees down to the too-low-to-notice level for the seller, and makes the fee transparent to buyer and seller both
[17:00:17] <jepler> but instead all we have is a system for turning coal into diamonds^Wbitcoin and greenhouse gases
[17:12:54] <pcw_home> Yeah thats an aspect of the bitcoin thing that seems really dumb
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[17:13:51] <pcw_home> I cant even buy xc6slx150s in 100s for the price of that card
[17:14:20] <pcw_home> avnets price in 100s is $150
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[17:29:45] <jepler> maybe it's old stock they'd love to unload after ASICs ate their lunch
[17:32:26] <pcw_home> maybe, and sometimes Xilinx has similar deals where they made a hugh number of one chip type for a customer
[17:32:27] <pcw_home> so some larger chips are cheaper than smaller chips
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[17:50:35] <pcw_home> Hmm whatever uspace uses for timing is pretty close (~50 PPM different from my 7I76Es 100 MHz)
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[17:53:02] <pcw_home> figured out why DPLL at 50 HZ wont work (prescale out of range: 0x01e8 written to 8 bit register)
[17:54:06] <pcw_home> dont think anyone (other than me) is crazy enough to try 50 Hz servo thread so not a real issue
[17:54:36] <micges-dev> so about 100Hz servo thread is minimum?
[18:02:05] <pcw_home> yeah thats a DPLL limit (well the driver could bound the prescale to 255 max and go lower but 50 Hz is a btt silly)
[18:02:49] <skunkworks_> hydraulic cylinder positioning machine? ;)
[18:03:21] <pcw_home> the driver attemps to normalize the parameters by setting the prescale but doenst check when out of prescale range
[18:04:19] <pcw_home> Actually linuxcnc has some issues at 50 hz servo thread also
[18:06:54] <pcw_home> got the "waiting for s axis" message a couple times
[18:08:04] <pcw_home> OK the stepgen works acceptably at 50 Hz (for some definition of acceptable) but not the DPLL
[18:09:03] <pcw_home> even with hydraulics theres no real disadvantage to a higher sample rate (maybe with filtering added)
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[18:34:20] <jepler> pcw_home: it's the clock called CLOCK_MONOTONIC, the description at
http://man7.org/linux/man-pages/man2/clock_gettime.2.html is the best one I've read
[18:35:33] <jepler> .. I think that this means it gets ntp's adjustments to frequency while it's locked, but shouldn't jump forward or back
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[18:46:31] <pcw_home> there's more description of the rate limiting in adjtime
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[18:50:57] <pcw_home> but no suggestion of the step size of the adjustments
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[19:02:28] <jepler> I think these days ntp uses
http://man7.org/linux/man-pages/man2/adjtimex.2.html
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[19:04:09] <pcw_home> So looks like a software DPLL
[19:05:00] <jepler> so to me the documentation says that CLOCK_MONOTONIC would be getting the adjustment from frequency offset, but not time offset
[19:05:13] <pcw_home> Yeah much better
[19:06:09] <pcw_home> I wonder if ubuntu enables ntp by default
[19:06:35] <jepler> I don't know
[19:06:44] <jepler> I think I've installed it manually on most of my recent debian machines
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[19:07:25] <pcw_home> I never saw an issue at 2 KHz on the test machine (stopped testing at about 120 days) but dont know if ntp was enabled
[19:08:18] <pcw_home> if its done with frequency adjustments it should be fine
[19:08:29] <jepler> ntp is not on the current debian live image
[19:09:30] <pcw_home> I have not tried that yet (couldn't get it to boot on any of my test machines)
[19:13:21] <pcw_home> amazing how well the stepgen works at 50 hz
[19:13:23] <pcw_home> a real stepmotor might object to only 5 frequency steps to full speed however :-)
[19:13:24] <jepler> it feels like every time it gets trickier to put together a working rtai kernel
[19:13:45] <jepler> I don't envy the guys who put in time doing that, but I'm thankful
[19:14:12] <pcw_home> Yeah that really looks like a struggle
[19:17:59] <pcw_home> related in a way to RT-net, the pain of using it (out of date drivers, main developer gone on to bigger and better things etc)
[19:18:00] <pcw_home> made it easer to try and figure out how to get along with some jitter
[19:18:06] <jepler> the 5 systems I checked with ntp installed have pll frequency offsets from about [-40 .. 100] ppm. excluding the ARM based one, [-40 .. 40].
[19:18:40] <pcw_home> so no problem
[19:19:11] <jepler> I have never looked at how close they stay in offset over time, though I've looked at 3 of these systems multiple times this week and I'm pretty sure they've all stayed in +-5ppm of some central value (leading digit not changing)
[19:20:45] <pcw_home> so this is a fully software clock? how does linuxcnc's thread get started by it?
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[19:22:58] <jepler> I think that way down the stack of turtles is a fixed frequency clock tied to an interrupt line (APIC or similar)
[19:24:04] <jepler> when I clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, {nanosecond-resolution-timestamp}) I *assume* that Linux uses its information about that clock relative to the ntp-tuned clock to set the right deadline
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[19:28:22] <jepler> I guess on the PC side, HPET is the current hotness. A 64-bit counter at at least 10MHz, plus at least 3 comparators
[19:28:40] <pcw_home> I assume RTAI must be all hardware interrupt timed
[19:29:44] <jepler> yeah ntu may know some gory details, but I know that you have to choose between APIC and 8254 timers at compile-time, so I think it oes low-level register touching
[19:30:01] <jepler> I wonder if it supports HPET, and/or if its non-support of HPET is an upcoming problem for rtai
[19:30:24] <pcw_home> Yeah (man those early Intel chips were horrible)
[19:30:38] <jepler> oes=does
[19:31:35] <pcw_home> 8254 and especially 8259 are nightmares
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[19:33:29] <jepler> so I suspect that for uspace, the HPET ends up being used in one-shot mode with the deadline set by converting from nanoseconds to HPET timer ticks
[19:33:48] <jepler> but I haven't had to plumb those layers at all, which is just fine by me
[19:34:18] <pcw_home> yeah as long as it works
[19:34:45] <CaptHindsight> I imagine that RTAI could use another available timer if HPET is not available
[19:36:24] <jepler> here's what the relevant bit of /proc/timer_list says while uspace is running a single thread:
http://paste.debian.net/120713/
[19:37:31] <jepler> there are also kernel APIs that let you schedule a wakeup somewhere in a time range, instead of asking for an absolutely specific time. this I guess groups wakeups which is good for battery usage on portables.
[19:37:35] <jepler> #5: <ffff8800a469bab0>, hrtimer_wakeup, S:01, schedule_hrtimeout_range_clock, xscreensaver/2524
[19:37:38] <jepler> # expires at 1833549285679750-1833549286380749 nsecs [in 1776754867 to 1777455866 nsecs]
[19:38:01] <jepler> so who knows why xscreensaver asked to be awakened within a range of 700999 nanoseconds, but apparently it did
[19:38:19] <pcw_home> ok so it does look like its used in one shot mode
[19:38:43] <CaptHindsight> NTU removed ~100K lines of dead code in RTAI to make it readable, it not really that complicated in concept, it's just having to wade though the years of patching without any cleanup
[19:39:23] <pcw_home> thats a lot of dead code
[19:39:45] <CaptHindsight> that has been the coding style at RTAI
[19:39:48] <pcw_home> doesn't look like there are any current ARM targets to RTAI
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[19:41:13] <CaptHindsight> nope, but if xenomai has a ipipe port to the ARM cpu then it's a really good start
[19:41:26] <jepler> even less call for rtai (instead of preempt-rt) on those devices, since you'd have to be daft to go the software stepgen route
[19:42:34] <CaptHindsight> with the hm2_spi and hm2_eth and the low cost of FPGA's it's not really worth the effort
[19:44:31] <CaptHindsight> NTU talked about RTAI for the A20 or imx6 if it really needed to be done to have Linuxcnc work on them
[19:46:54] <CaptHindsight> I still want to try imx6 with 6i25 PCIe
[19:47:59] <CaptHindsight> imx6 and A20 both have on chip ethernet as well, so hm2_eth on both look promising
[19:48:05] <jepler> 7i90's price is so right, except for how you have to fabricate a different adapter board for every different arm board
[19:48:45] <pcw_home> well theres a 7I91
[19:48:59] <CaptHindsight> you won't have to with ethernet
[19:51:02] <CaptHindsight> NTU has the cubie2 and the 7i91, I have to fix the 5V power issue on the CB2
[19:51:14] <pcw_home> I tried to get the 7I92 price down to 7I90 level but its hard with dealer margins and middling volumes
[19:53:58] <CaptHindsight> I get the part numbers confused, 7i90 is LPT/SPI SSI,BISS and the 7i92 is ethernet?
[19:54:31] <pcw_home> Yes 7I92 is Ethernet 5I25 effectively
[19:54:46] <pcw_home> (same connectors and FPGA)
[19:55:30] <pcw_home> 7I90 is EPP/SPI/RS-422 Serial/SSremote
[19:55:51] <pcw_home> RS-422 SSremote
[19:56:08] <CaptHindsight> I don't see the 7i92 at the store
[19:56:49] <pcw_home> its not available yet (soon though proto is fine +- a few wires)
[19:57:13] <CaptHindsight> ah ok, I had it confused with the 7i90
[19:58:48] <CaptHindsight> so cubie2 and any of the imx6 boards with ethernet might just work with the 7i92
[19:59:51] <CaptHindsight> pcw_home: is there an easy way to test hm2_eth without a 7i92?
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[20:01:11] <pcw_home> any of the Ethernet cards will do (7I80HD, 7I80DB 7I76E)
[20:03:23] <pcw_home> the code is the same in all
[20:05:48] <CaptHindsight> now that the new AMD apu's are working out pretty well except for the hardware gpu driver we are trying to find something ARM that makes sense to use
[20:08:51] <pcw_home> where you need something small thats built in or where cost in volume is an issue
[20:08:53] <pcw_home> usually power consumption is not an issue if you have a motion system unless its portable (robotics?)
[20:09:32] <CaptHindsight> built into a touch panel
[20:09:44] <CaptHindsight> power is not the issue, it's more space
[20:10:38] <CaptHindsight> the feedback from the laboratory automation and robotics was "take up less counter space"
[20:11:52] <pcw_home> Ethernet and Preemt-RT widen the CPU choice considerably
[20:12:05] <CaptHindsight> those all-in-one PC's don't have PCIe
[20:12:23] <CaptHindsight> USB and ethernet is what they mostly offer
[20:13:26] <pcw_home> some will have minipcie
[20:14:20] <CaptHindsight> plus they are mainly consumer
[20:14:44] <CaptHindsight> we need a industrial panel PC
[20:14:52] <CaptHindsight> easy enough to make
[20:15:08] <pcw_home> if 1 KHz update is good enough Ethernet is probably the best
[20:15:19] <CaptHindsight> it's looking that way
[20:15:47] <CaptHindsight> and imx6 has PCIe and a decent GPU
[20:17:20] <pcw_home> PCIE is great but unless you use non-standard cabling, external PCIE is an expensive solution
[20:17:50] <pcw_home> (is is possible to use cat5 ...)
[20:18:22] <pcw_home> but you are distance limited
[20:19:20] <CaptHindsight> http://www.microcenter.com/product/429195/Pavilion_20-b323w_20_All-in-One_Desktop_Computer_Refurbished something like this is ok in a lab, but not in a shop
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[20:20:59] <CaptHindsight> it's generally under 1m (or in the same enclosure) and 2m max from PC to FPGA
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[20:24:00] <CaptHindsight> recently I've just been using a 12" PCIe slot extender cable
[20:25:38] <CaptHindsight> bitcoin mining with GPU's has brought the prices down to a few $
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[21:55:28] <jepler> I wonder what's actually going on with this user who says his disk runs the whole time linuxcnc is going
[21:55:37] <jepler> (on the -users list)
[21:57:42] <pcw_home> I have not seen anything like that
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[23:59:18] <NTU> whats the RTAI question for me?