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[00:08:26] <kwallace1> I would tend to agree and hope that the information on the net will save me time in getting them hooked up. I'll post my results, but it may take a week or two.
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[01:41:51] <jepler> after 10ksec of latency-histogram, my odroid's latency is <40us
[01:42:12] <jepler> but as soon as I try to talk on the spi bus in realtime, the latency goes to hell, so it's not "useful" latency
[01:42:31] <jepler> this is actually better than my earlier test, probably due to using isolcpus=3 now
[01:43:11] <jepler> kwallace1: cool
[01:44:17] <jepler> memleak: hmph, you caught me: I didn't even bother to compile it that way
[01:44:28] <jepler> let alone load any modules
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[02:11:41] <memleak> heh!
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[02:25:26] <skunkworks> kwallace1: I think in the smithy configs there is an example of communicating to a digital caliper...
[02:38:20] <skunkworks> you may have to ask matt.. I am not seeing it but remember him talking about it\
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[03:47:36] <memleak> jepler, this is as close as I could to get your commit to work:
https://github.com/NTULINUX/RTAI/commit/d2deb6292b258775b48469c58fb9d26a1cb73be0
[03:49:01] <memleak> you think its re-written enough?
[03:51:31] <memleak> also any idea why i keep getting "x.hex.high is used uninitialized in this function" ? what does x.hex.high mean so i can initialize it within the function its in?
[03:52:52] <memleak> it isnt defined anywhere, i assume its something that comes from somewhere in here:
https://github.com/NTULINUX/RTAI/blob/master/base/math/fp.h#L7
[03:53:04] <memleak> not much of a C expert as you can probably tell...
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[06:29:43] <memleak> kms on radeon r9 290 (volcanic islands) has no bad latency spikes..
[06:30:33] <memleak> so if you want 3D + good RTAI performance, get a 500 dollar GPU... :/
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[12:45:31] <jepler> memleak: not really, you still copied parts of the non-distributable file verbatim
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[13:43:53] <jepler> memleak: new pull request offered. this one I built and got no modpost undefined symbol errors
[13:44:41] <memleak> jepler you're an amazing coder, thanks
[13:45:51] <memleak> will merge
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[14:05:04] <jepler> I'm an experienced coder who knew what to grep for in the gcc manual pages
[14:05:36] <jepler> memleak: anyhow, you're welcome; I hope this iteration works better than the last one
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[14:07:55] <jepler> overnight latency-histogram on the odroid is +-40us @ 1ms
[14:08:10] <jepler> having run for 40k seconds
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[14:13:54] <jepler> "Kernel panic - not syncing: timer doesn't work through interrupt-remapped IO-APIC"
[14:14:21] <jepler> memleak: so my kernel built from 3.14.16 plus the patch from your RTAI doesn't boot :-/
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[15:25:11] <jepler> pretty sure it's spidev itself that has bad latency. with the odroid as the master, merely not having a properly behaving slave couldn't change the timing of spidev.
[15:26:04] <jepler> so I wrote a component that does simple 64-bit spi transactions on /dev/spidev without expecting anything in particular in response.. and predictably, it gets realtime deadline errors
[15:26:37] <jepler> the functions max-time rises to nearly 4ms after just a few seconds
[15:27:21] <jepler> +'
[15:29:00] <pcw_home> SPI masters dont have any data dependence so they dont even know if the slave is there
[15:29:07] <jepler> pcw_home: right
[15:29:42] <jepler> hostmot2 *does* do something exceptional if it starts getting crazy data read back, though, so I needed this simpler component to confirm it was the kernel spi device alone that causes the problem
[15:32:06] <pcw_home> where everything is encapsulated in one packet like Ethernet, there probably should be some sanity checks built in
[15:33:09] <pcw_home> (say read the cookie or write a sequence number on writes thats checked on reads)
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[15:34:01] <pcw_home> not sure if the overhead is worth it or not on SPI
[15:34:29] <jepler> in spi, a basic minimum check would be if that first returned word is all AAs
[15:34:54] <jepler> when the connection is bad, spi reads as all bits one, which seems to cause an immediate watchdog bite report
[15:35:03] <Tom_itx> why AA and not FF?
[15:35:42] <jepler> Tom_itx: when properly working, the first byte the SPI-attached mesa card shifts out is AAAAAAAA
[15:35:45] <jepler> just because it is
[15:35:59] <Tom_itx> gotcha.. figured that out after the enter key :)
[15:36:24] <pcw_home> its left over debug code (it could actually be anything)
[15:37:56] <pcw_home> better for the driver to complain about SPI connection issues than proceeding with garbage data
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[15:44:26] <jepler> pcw_home: would you have room for a crc32?
[15:45:30] <jepler> the idea's not quite baked, but: Imagine that the reply to each command after the first is the crc of the whole transaction up to that point
[15:46:19] <jepler> now the linuxcnc side could just tack an extra "read zero bytes at 0000" command at the end and check that the CRC matches
[15:48:09] <jepler> but you'd have to have the CRC available really quick
[15:49:01] <pcw_home> CRC done bit by bit is available immediately
[15:50:38] <pcw_home> currently I think the 0xAAAAAAAA is only at start of frame
[15:50:41] <jepler> yes
[15:50:55] <jepler> elsewhere it reads back zeros for the words that are commands
[15:51:36] <jepler> maybe instead it could do something like read back the CRC32 of the received data XOR CRC32 of the sent data, or the CRC16 of the received data concatenated with the CRC16 of the sent data
[15:52:45] <jepler> at 32MHz, reading back that checksum would add just another 1us to a transaction
[15:56:20] <jepler> ugh ugh ugh gross: every spi transaction maps and unmaps dma memory
[15:58:51] <pcw_home> Yeah, using the general purpose SPI driver is like watch repair with a Swiss army knife
[16:02:30] <jepler> though in the case of my simple transfer program, the amount of data transferred is just 8 bytes per direction and the code reads like it's supposed to use a FIFO instead of DMA when the amount of data to transfer is small
[16:03:32] <jepler> fifo is maybe 0x1ff or 0x7f .. bytes? words?
[16:06:02] <pcw_home> I would expect that the SPI hardware has a small FIFO (the Alwinner A10/20 and TI Sitara SPI hardware is like that)
[16:06:55] <pcw_home> I think the A10 is 64 bytes, beyond that it can use demand mode DMA
[16:07:42] <pcw_home> (to keep the TX FIFO filled and RX FIFO emptied)
[16:08:24] <CaptHindsight> same depth 64 in the Exynos
[16:08:34] <jepler> > Two independent 32-bits wide transmit and receive FIFOs: depth 64 in port 0 and depth 16 in port 1 and 2
[16:09:15] <jepler> > SPI controls the number of packets to be received in master mode. Set SFR (PACKET_CNT_REG) to receive any
[16:09:18] <jepler> number of packets. SPI stops generating SPICLK if the number of packets is similar to PACKET_CNT_REG.
[16:09:21] <jepler> "similar to" ??
[16:09:39] <pcw_home> :-)
[16:10:59] <CaptHindsight> "in my mind" it probably means "the same" or =
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[16:37:07] <memleak> jepler, i had that problem too
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[16:39:43] <memleak> one sec. its a kernel config issue
[16:40:34] <jepler> of course it is
[16:40:59] <memleak> i know which options roughly
[16:41:23] <memleak> however i dont know which one specifically so i disable a set
[16:43:07] <jepler> if there are some options that are forbidden when ipipe is selected, can't that be expressed in the Kconfig language?
[16:43:19] <jepler> rather than just carrying around information in your head
[16:43:36] <memleak> im going to post it
[16:43:42] <memleak> and adjust .patch soon
[16:44:09] <memleak> give me a minute and ill write it up
[16:46:03] <memleak> dpaste.com/02AFGWJ
[16:46:41] <memleak> i turned all those off at once and it fixed the issue for me. i think its just IOMMU and the PCI options
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[16:47:06] <memleak> it will need trail and error which im really not in the mood for atm
[16:47:10] <memleak> *trial
[16:48:24] <memleak> i dont want to adjust .patch file until i know which exact options cause it
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[17:09:15] <memleak> just turning off PCI IOAPIC doesnt do it
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[17:24:36] <memleak> its IOMMU that causes it
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[17:41:49] <jepler> memleak: "Disable IOMMU Hardware Support" ?
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[17:43:58] <memleak> git pull and patch kernel source with updated hal-linux patch
[17:46:29] <memleak> ill do the same for 3.10 if successful for you
[17:46:40] <memleak> (works here)
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[17:48:33] <memleak> jepler, are you using SMP?
[17:49:33] <jepler> memleak: yes
[17:50:16] <memleak> 32 or 64?
[17:50:40] <memleak> also you'll need SSE2
[17:50:42] <cradek> > if you just want to make a rip cut you must have a DXF of a straight line to import
[17:51:23] <memleak> i havent tested compilation on 32-bit yet
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[17:57:58] <jepler> well, it did turn off a bunch of config options
[17:58:27] <jepler> I notice one of them is -CONFIG_IRQ_REMAP=y
[17:58:39] <jepler> which could be related to "timer doesn't work through interrupt-remapped IO-APIC"
[17:59:58] <memleak> thats related to IOMMU
[18:00:04] <memleak> all IOMMU must be off
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[18:07:27] <jepler> do you understand why it's incompatible, or just that it *is* incompatible?
[18:10:39] <memleak> https://lkml.org/lkml/2012/8/7/558
[18:11:09] <memleak> that "fix" either isnt present or doesnt do anything when ipipe is enable
[18:11:20] * memleak checks source
[18:11:55] <memleak> its present.
[18:13:26] <memleak> http://www.xenomai.org/pipermail/xenomai/2012-September/026228.html
[18:14:17] <memleak> ah i see it i think..
[18:14:48] <memleak> in your ipipe enabled kernel look at line 1251 in arch/x86/kernel/io_apic.c
[18:15:10] <memleak> compare that code to the code in the xenomai email i posted
[18:16:49] <memleak> "mark the free vectors" is handeled differently
[18:19:48] <jepler> ok thanks for the explanation
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[18:21:13] <memleak> you betcha!
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[19:00:51] <memleak> oh. i see what you meant.. sorry..
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[19:48:05] <jepler> pcw_home: is there some reason I couldn't use a 10P IDC cable & connectors for 7i90?
[19:50:14] <jepler> I guess the 26p cable is now plentiful as a "raspberry pi gpio cable"
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[19:58:36] <pcw_home> IDC connectors smaller than the deign size run into adjacent pins
[19:58:44] <pcw_home> design size
[19:59:41] <pcw_home> (due to the added width of the mechanism that hosts the 2 pieces together)
[19:59:50] <jepler> aha
[20:00:02] <jepler> I'm surprised I don't recall having found that out the hard way
[20:00:08] <pcw_home> you can use the individual wire blocks but then you have to get the right crimper
[20:01:13] <pcw_home> no reason you cant crimp 10 pin cable in a 26 pin IDC connector though
[20:01:52] <jepler> true
[20:03:36] <jepler> so the general shape of the odroid u3 is the same as their "IO shield", with these two 2mm connectors at the top
http://dn.odroid.com/homebackup/U3%20IO%20SHIELD%20REV0.3.png
[20:03:55] <pcw_home> Thats how I tested the 7I90 SPI interface
[20:03:56] <pcw_home> 7I80HD --> 50 hdr --> 10 pin cable --> 26 hdr --> 7I90
[20:04:46] <jepler> I'm trying to decide whether to get the mechanical part OK I need to make my board as big as that (to use 4 holes for stability) is necessary, or whether to just make the board big enough to go to the top two screws (smaller, cheaper board)
[20:05:15] <archivist> compromise, 3 screws
[20:05:32] <jepler> archivist: the board house I'll use costs by the smallest enclosing rectangle, so I don't think I save
[20:05:47] <pcw_home> the 4 and 8 pin 2mm headers are the I/O connectors?
[20:05:52] <jepler> pcw_home: right
[20:06:18] <archivist> or something I saw inside a month or two ago, two screws and an application of a glue gun
[20:06:36] <jepler> they're on the bottom of the main board, so my board sits under it and the .100" header sticks out from that edge of the board
[20:06:57] <archivist> it was the high voltage flash supply in kids camera
[20:08:18] <jepler> archivist: nice work, they must have saved pennies that way
[20:08:26] <pcw_home> Hmm long enough for a couple 50 pin headers and a FPGA
[20:08:46] <jepler> pcw_home: don't start seeing a product in your mind's eye yet
[20:10:23] <jepler> anyway, the first tiny little board without any mounting provision ended up sitting like this, so it's easy to understand in retrospect why the female connectors on the u3 aren't happy anymore:
http://emergent.unpythonic.net/files/sandbox/IMG_20140823_150751_027.jpg
[20:10:36] <jepler> so I'm thinking .. yes, enough board so it mounts at 4 points
[20:12:08] <pcw_home> Yeah misalignment is tough on the connectors
[20:13:03] <jepler> too bad shrouded 2mm male headers don't seem to be a thing
[20:14:06] <pcw_home> they are available but usually for IDC cables
[20:15:45] <pcw_home> not common for board-to-board (and dont help lengthwise alignment since the are sized for the longer IDC connectors)
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[21:10:33] <jepler> I feel very guilty about all this unused board area
http://emergent.unpythonic.net/files/sandbox/oddspi.png
[21:11:54] <pcw_home> needs a FPGA
[21:14:11] <jepler> from time to time I contemplate the idea of putting a hostmot2 firmware on a non-mesa card
[21:14:14] <jepler> .. but why would I?
[21:14:58] <jepler> "so that there's an Open Hardware mesa board" is an idea that tickles my fancy a bit
[21:15:08] <jepler> er, "open hardware hostmot2 board" I should say
[21:15:19] <pcw_home> its probably quite portable to any Xilinx FPGA
[21:16:04] <pcw_home> I am looking at trying to port it to the lattice ICE 40 series for lower cost simple things
[21:16:51] <jepler> are there many xilinx-specific bits?
[21:17:15] <pcw_home> Yes there are some xilinx primitives
[21:17:35] <pcw_home> SRL16s and DCMs mainly
[21:18:53] <pcw_home> probably some ways to genericise them
[21:23:09] <jepler> http://opensource.zylin.com/zpu.htm 442 LUT @ 95 MHz after P&R with 32 bit datapath and 32kBytes BRAM(example using Xilinx part).
[21:25:01] <jepler> stack based with some ops via microcode
[21:26:04] <jepler> bbl
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[21:33:52] <pcw_home> Ive looked at the ZPU but its really really slow
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[21:43:14] <cmorley> pcw_home: do dome 7i77 and 7i76 not have encoder counters in a different mode?
[21:44:35] <cmorley> pcw_home: i mean the x1 encoder counters
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[21:56:49] <pcw_home> the MPG inputs on the field I/O default to 1x mode
[21:57:59] <pcw_home> the normal high speed hostmot2 encoder counters have 4x and step/dir mode (no 1x mode)
[21:59:29] <pcw_home> 1x mode makes sense for MPGs since you may want 1 count per detent
[21:59:31] <pcw_home> (and count between detents so its hard to "tease")
[22:01:34] <pcw_home> I think all 24 possible count modes are available via per channel EEPROM setup variables
[22:01:35] <pcw_home> But I think this is somewhat purposely undocumented
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[22:15:37] <pcw_home> If you are asking about whether the MPG encoders are there, firmware versions before 12 didnt have the encoders
[22:15:39] <pcw_home> so the 7I76/77 remote firmware should be upgraded
[22:16:16] <pcw_home> (there is a script for doing this)
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[22:27:51] <memleak> my email isnt going through >:(
[22:28:01] <memleak> wrong channel
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[23:29:06] <cmorley> pcw_home: I suppose the firmware version is shown in dmesg. is the script to upgrade the 'mesaflash' program?
[23:29:56] <cmorley> It would be nice to have x1 mode on hi-speed encoders too.
[23:31:16] <cmorley> I am updating pncconf trying to add the modes that include the field IO MPG counters - when I went to test on my hardware - there are no counters. I guess I need to update them. Thanks.
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