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[00:00:42] <linuxcnc-build> build #1351 of checkin is complete: Failure [4failed] Build details are at
http://buildbot.linuxcnc.org/buildbot/builders/checkin/builds/1351
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[00:30:44] <linuxcnc-build> build #1354 of lucid-i386-sim is complete: Failure [4failed git] Build details are at
http://buildbot.linuxcnc.org/buildbot/builders/lucid-i386-sim/builds/1354 blamelist: Andy Pugh <andy@bodgesoc.org>
[00:30:45] <linuxcnc-build> build #1358 of hardy-amd64-sim is complete: Failure [4failed git] Build details are at
http://buildbot.linuxcnc.org/buildbot/builders/hardy-amd64-sim/builds/1358 blamelist: Andy Pugh <andy@bodgesoc.org>
[00:30:47] <linuxcnc-build> build #1353 of lucid-rtai-i386-clang is complete: Failure [4failed git] Build details are at
http://buildbot.linuxcnc.org/buildbot/builders/lucid-rtai-i386-clang/builds/1353 blamelist: Andy Pugh <andy@bodgesoc.org>
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[00:59:35] <linuxcnc-build> build #1352 of checkin is complete: Failure [4failed] Build details are at
http://buildbot.linuxcnc.org/buildbot/builders/checkin/builds/1352 blamelist: Andy Pugh <andy@bodgesoc.org>
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[14:42:00] <skunkworks> pcw_home, as I was drifting off to sleep I was thinking about your pll you are working on.. From what I gathered it is so - the (lets say the 7i80) can just send linuxcnc the data without being asked for it. So - how does it know when to send it when the jitter of the servo cycle can be + and - of the target period
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[14:49:33] <pcw_home> The current (R14) firmware ist still completely master slave (or equivalent PC term)
[14:49:35] <pcw_home> but it can delay parsing of packets either with a time delay or waiting for a selected DPLL timer
[14:49:36] <pcw_home> so for a 2 packet mode, when the HostMot2 write packet is sent, that packet has:
[14:49:38] <pcw_home> 1. write (output) data
[14:49:39] <pcw_home> 2. wait for DPLL
[14:49:41] <pcw_home> 3. read commands
[14:50:43] <pcw_home> This does require that you read everthing you may need (since the read command is from the previous cycle)
[14:51:51] <pcw_home> DPLL jitter shoud be in the couple or uSec region assuming quite bad host jitter (say 120 usec)
[14:52:03] <pcw_home> couple of uSec
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[14:54:37] <pcw_home> the DPLL does 2 things:
[14:54:39] <pcw_home> 1. Sample time jitter reduction
[14:54:40] <pcw_home> 2. Allow read pretrigger to absorb wire/parsing delays
[14:54:42] <pcw_home> and delays of slow hardware (sserial, SSI,BISS.Fanuc,SPI etc etc)
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[15:48:24] <seb_kuzminsky> linuxcnc-build: force build --branch=master checkin
[15:48:25] <linuxcnc-build> build #1353 forced
[15:48:25] <linuxcnc-build> I'll give a shout when the build finishes
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[16:46:54] <seb_kuzminsky> ok, the buildbot is building again
[16:47:10] <seb_kuzminsky> not the right fix, but a bandaid to get things moving again :-/
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[16:50:20] <linuxcnc-build> Hey! build checkin #1353 is complete: Success [3build successful]
[16:50:20] <linuxcnc-build> Build details are at
http://buildbot.linuxcnc.org/buildbot/builders/checkin/builds/1353
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[17:17:03] <jepler> seb_kuzminsky: thanks for your work on buildbot
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[17:19:34] <IchGuckLive> jepler: what is changing i see lots of failues is there some new
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[17:52:28] <IchGuckLive> micges: i uploaded the english version
http://www.youtube.com/watch?v=zLXDc1aFmxg
[17:56:21] <andypugh> I _think_ you could halcmd the same HAL file as was used to load the gamepad originally, if it was in a separate file.
[17:56:46] <andypugh> (My gamepad tends to disappear sometimes too)
[17:57:08] <seb_kuzminsky> linuxcnc-build: force build --branch=v2.5_branch checkin
[17:57:09] <linuxcnc-build> build forced [ETA 1h01m55s]
[17:57:09] <linuxcnc-build> I'll give a shout when the build finishes
[17:57:11] <IchGuckLive> you only need to reload the connections not the halfile
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[17:57:27] <IchGuckLive> and also you cand use the nice direction signes in the halcmd
[17:57:39] <andypugh> halcmd -f gamepad.hal (and then have HALFILE=gamepad.hal in the INI)
[17:58:16] <IchGuckLive> i try
[17:58:52] <IchGuckLive> the hint is that you need to initial the usb first then relconnect it
[17:58:57] <andypugh> There is no real advantage, except that if you update there is only one file to edit.
[17:59:02] <IchGuckLive> if you do in one step in one file it wont work
[17:59:19] <andypugh> Even with loadusr -W ?
[17:59:41] <IchGuckLive> need to rey this also
[18:00:11] <IchGuckLive> try B)
[18:01:07] <micges> IchGuckLive: glad it works
[18:01:22] <IchGuckLive> ;-)
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[19:13:09] <linuxcnc-build> Hey! build checkin #1354 is complete: Success [3build successful]
[19:13:09] <linuxcnc-build> Build details are at
http://buildbot.linuxcnc.org/buildbot/builders/checkin/builds/1354
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[19:56:21] <mhaberler> I would have to plug the 5i25 into the amd, but I could try
[19:56:28] <mhaberler> any research issues here?
[19:57:01] <skunkworks> you had a video of the mesa card running - what system was that?
[19:57:10] <mhaberler> an atom
[19:57:30] <skunkworks> what os?
[19:57:39] <mhaberler> any os these days ;)
[19:57:52] <skunkworks> heh - 32/64?
[19:57:57] <mhaberler> 32
[19:58:11] <skunkworks> ah. PCW is wondering if it will work on 64
[19:58:37] <mhaberler> well I can try, not sure anybody did so far
[19:59:36] <skunkworks> right - I have only done the rtnet stuff in 64bit
[19:59:57] <skunkworks> bbl
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[20:00:28] <PCW> Just wondering if the PCI access scheme will work on 64 bit (I would expect mesaflash Ethernet access to work on pretty much anything)
[20:00:43] <mhaberler> right, that needs a look
[20:01:13] <micges> skunkworks: that's great
[20:01:30] <micges> I don't have any 64 bit system atm
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[20:22:48] -hitchcock.freenode.net:#linuxcnc-devel- [freenode-info] if you're at a conference and other people are having trouble connecting, please mention it to staff:
http://freenode.net/faq.shtml#gettinghelp
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[20:29:34] <mhaberler> ubc3 runs the hm2-stepper config with an 5i25 just fine on an amd64, os=3.10.4 rt-preempt
[20:30:07] <cradek> awesome
[20:30:51] <mhaberler> were there any problems with that? probably just no amd rtai kernel, I guess?
[20:30:54] <cradek> we've seen hm2 stepgen being kind of brittle in the face of big latencies - do you see that?
[20:31:11] <mhaberler> how would I tickle that?
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[20:31:55] <cradek> that's a good question, I don't remember even what the symptoms were
[20:32:00] <PCW> rt-preempt ought to :-)
[20:32:17] <cradek> PCW: do you remember how the problem shows up?
[20:32:37] <PCW> following errors
[20:32:46] <PCW> wacky motion
[20:32:56] <cradek> so it just falls behind, or is it weirder?
[20:33:44] <mhaberler> note this rt-preempt kernel is pretty good as far as rt-preempt kernels go, barely above 20-25uS latency
[20:34:03] <PCW> You wont see a problem there
[20:34:27] <cradek> wow, that is good
[20:36:10] <mhaberler> no following errors, and nothing suspicious in the log
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[20:36:29] <cradek> mhaberler: any progress (or new obstacles) on jogging?
[20:37:26] <PCW> Basically the issue is with the hm2 stepgen driver is that the hardware stepgen has better short term
[20:37:28] <PCW> timing than the host but the driver does these huge velocity corrections based on the assumption
[20:37:30] <PCW> that the servo period is constant
[20:37:31] <mhaberler> nothing fundamental; I've switched to the ja3 branch and it is a complex merge which I need to redo because I goofed somewhere
[20:38:49] <jepler> mhaberler: I apologize that I haven't taken the time to review that code you sent me the other day. If I don't have time today, I am afraid I won't have time before the weekend. :-/
[20:38:58] <mhaberler> sure!
[20:39:12] <mhaberler> that one has been around so long a week dont matter
[20:39:42] <jepler> as for putting the jog-while-paused work on ja3, you might at least check whether rebasing it would go better than merging
[20:39:46] <mhaberler> actually if you have a peek - the patch is rather minimal except for interpmodule.cc which is a wasteland of wraooers
[20:39:56] <mhaberler> I tried both
[20:40:08] <mhaberler> it's just a single file, and I need to do it more carefully
[20:40:09] <jepler> well let me give it ten minutes since I'm here
[20:41:04] <mhaberler> I would really be curious if the segfault is gone; I am not totally sure if the gcodemodule unload triggers the dtor, or what else
[20:41:12] <jepler> (though at the moment I can't access the machine where I routinely saw the crash, it's suspended)
[20:41:21] <mhaberler> ha
[20:43:09] <andypugh> PCW: What is the difference between readin 0x7100 and 0x7600 ?
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[20:45:03] <PCW> reading 0x7100 just reads the DPLL accumulator, reading 0x7600 reads the accumulator _and_ syncs the DPLL
[20:45:40] <andypugh> OK, so it makes sense to only read one of them. Grand.
[20:45:52] <PCW> so unless you need it for timing something, a single read of 0x7600 is all thats needed
[20:46:40] <andypugh> As for dpll being first, as things stand the modules are parsed and registered for read-write in the order that they appear in the idrom.
[20:47:16] <PCW> OK I can put it first
[20:48:05] <PCW> Still cant get the funuc stuff to work though the DPLL timer start fanuc read works with my windows test fixture
[20:49:21] <PCW> I also fixed a few bugs (SSI,Fanuc,BISS were all triggered off the wrong edge of the timer so off by 1/2 servo period)
[20:49:39] <micges> PCW: what was the test you did to see 64Hz I/O frequency on windows? ping or some scripted test?
[20:49:52] <micges> PCW: (with 7i80
[20:49:59] <PCW> just my dpll test loop
[20:50:32] <micges> from python?
[20:50:38] <PCW> it may be driver specific (some 1G card it this machine)
[20:50:46] <PCW> Pascal
[20:50:54] <micges> ah ok
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[20:52:09] <PCW> also global busy bits for BISS, SSI, Fanuc have changed so they are gated with DAV
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[20:53:00] <PCW> so the hardware says its busy if a transfer is in progress or the data is stale (already been read)
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[20:53:50] <mhaberler> PCW: identical result with xenomai 3.5.7/amd64 ; just reboot, _no rebuild_, ha
[20:54:29] <andypugh> PCW: What frequency do you end up with the fanuc runnning at?
[20:54:33] <PCW> Thats great!
[20:54:58] <PCW> On linuxcnc? 2 KHz
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[20:55:21] <PCW> but its not running for some reason (no request pulse)
[20:56:40] <PCW> the timer start bit is set. and the DPLL is running, will have to raw read some other registers to see whats gone wrong
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[20:57:59] <skunkworks> logger[mah]:
[20:57:59] <logger[mah]> skunkworks: Log stored at
http://linuxcnc.mah.priv.at/irc/%23linuxcnc-devel/2013-10-01.html
[20:59:37] <JT-Shop> changing K from 0.050 to 0.750 does not give the expected Z depth change but does break the tap very fast and very lout
[20:59:38] <JT-Shop> d
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[21:00:44] <andypugh> You needed a coarser tap.
[21:01:52] <JT-Shop> very much, or just change Z like I wanted to
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[21:02:16] <PCW> andypugh: which bitfile are you testing with? I'll make up a fresh one
[21:02:20] <JT-Shop> I did get everyone on the network now... windoze was causing the problem somehow
[21:02:57] <PCW> not terribly surprising
[21:03:24] <andypugh> PCW: Currently working with mixedabs.bit
[21:06:37] <PCW> on what FPGA card?
[21:06:53] <andypugh> 6i25
[21:08:13] <jepler> mhaberler: I am scratching my head as to how your solution fixes the zero-initialization of the contents of _setup, but I didn't see any problems that seemed to be the result of lack of initialization (unlike my change)
[21:08:59] <mhaberler> because I explicitly call the constructed ctor?
[21:09:30] <jepler> well my understanding of C++ was that it didn't make a difference, the zero-arg constructor is the one you get by default
[21:09:34] <mhaberler> (to be honest: not sure either ..)
[21:10:03] <mhaberler> maybe we should look at the .s file
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[21:25:40] <jepler> well I just spent some time with my copy of stroustroup but was unenlightened
[21:26:19] <jepler> absent chapter and verse I would feel *better* with the hundred or so zero-initializations it would be necessary to write
[21:26:24] <jepler> but if it's testing OK I can live with it
[21:27:58] <jepler> here's my assertion and test that exercises it:
http://emergent.unpythonic.net/files/sandbox/test-gcodemodule-invariant.patches.mbox
[21:28:04] <jepler> fails on 10.04 before your changes, passes afterwords
[21:28:05] <jepler> bbl
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[21:38:30] <jepler> Stroustrup 10.4.2 "Default Constructors" states that in the default constructor of a class type, its base classes and its members of class type are initialized, and a field of e.g., type int is not
[21:39:01] <jepler> there's not a constructor defined for setup_struct, so what we get is the default constructor
[21:40:11] <jepler> (that's paraphrasing _The C++ Programming Language Special Edition_
[21:40:13] <jepler> )
[21:40:15] <jepler> bbl really this time
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[21:50:50] <mhaberler> that test is neat, I'll steal it
[22:07:56] <mhaberler> I've merged master into ja3, should I push that?
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[23:41:53] <rellenberg> Hi everyone. I'm Rob Ellenberg, and I posted the proposal a few days back about queue lookahead.
[23:42:16] <rellenberg> I'm new to IRC, so I just figured I'd jump on and see if anyone had questions or comments about the idea
[23:42:16] <andypugh> Hi. Is it finished yet :-?
[23:42:24] <rellenberg> lol, if only
[23:42:33] <micges> rellenberg: hi
[23:42:56] <andypugh> pcw_home: Does 7uS dither in the DPLL seem right?
[23:45:17] <andypugh> Ah, not dither, that's the offset. By tweaking the base frequency it is down to zero.
[23:45:47] <andypugh> rellenberg: You are maybe a little late to catch mah, or any other euros.
[23:47:09] <rellenberg> Ok, good to know
[23:47:27] <cradek> hey, welcome
[23:47:38] <rellenberg> Do you guys do periodic meetings via IRC?
[23:48:08] <cradek> yes for official decisions. but for the real work it's ad-hoc.
[23:48:45] <cradek> pardon my phone typing...
[23:49:41] <cradek> see the Meeting* pages on wiki.linuxcnc.org if you are interested in that process. we recently started doing that.
[23:50:28] <rellenberg> Thanks! I'd at least like to follow the decisions so I don't end up stepping on toes with my code
[23:51:56] <cradek> you won't unless you get really wild... the only consideration to keep in mind is it's easier for people to evaluate changes if you do one thing at a time on a branch. we love our feature branches for integration.
[23:53:26] <KGB-linuxcnc> 03andy 05ssi-fanuc-biss-dpll 06a4e89 06linuxcnc 10docs/man/man9/hostmot2.9 10src/hal/drivers/mesa-hostmot2/hm2_dpll.c 10src/hal/drivers/mesa-hostmot2/hostmot2.h * Triggering on the right function, better defaults, some pin changes, and docs
[23:54:25] <cradek> I'm going to head home so I have a keyboard. think you'll be around for a bit?
[23:54:45] <rellenberg> I'll be on till about 8:30 EST tonight
[23:55:36] <andypugh> Whereas I will be here until 0055 BST. Which is now. Night all!
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