skunkworks: thanks for mentioning it
Thank you ;)
Last time you could not get in :)
05:38:14 up 1 day, 3:06, 3 users, load average: 12.29, 8.50, 9.01
did anyone find a Z-N formula table that they trusted?
jepler: no - I tried a few of the formulas with mass added to the servo and none seemed to work.
(but it could have been me)
I was hoping to try the auto-tune pid. I think petev checked in a fix so I may try it agian tonight.
I did do 'ok' manually tuning. but I still don't know what I am doing.
-Modified PID calculations to calculate PID values appropriate for EMCs
PID equation. The PID equation they were intended for is slightly different.
This is a comment in petev at_pid
I wonder what he used..
looking at the code - looks like I is still calculated by period/2 and and D is calculated by period / 8
hmm - looks like is it just ultimate gain * .6
* skunkworks muddling thru the code
although - ultimate gain is calculated by (4*effort)/(PI*avgaplitude)
sure seems like not much code for all it does ;)
(pid in general)
yeah it is pretty magical
does it work after his fix last night?
I have not tried it - tonight
the "ultimate gain" is the P where the oscillation has gain=1 over successive cycles (does not grow out of control or die out) -- so if you don't find exactly this gain, you have to use some method to find it based on the oscillation amplitude at the second peak. sounds like petev's using some kind of average to do this..
Spookyness at a distance
cool. the 5i22 is out now
or it will be at the end of the week, anyway
unfortunately, it'll be >2x the cost of a 5i20 ($439, I think)
1 more header worth of I/Os?
+ 1.5M gates in the FPGA
and it'sa faster FPGA afmily as well
family, that was
until I hear from jmkasunich that he's feeling a pinch, I'm not worried about that
didn't he say that 12 stepgens used ~70% of the 5i20?
or was that 16 stepgens
what use is 12 (or 16) stepgens?
err - for testing how big the FPGA is?
he did that to see how constrained the FPGA would be
the 5i22 could likely handle a fully generic PWM+stepgen model: every pin could be an I/O or any pair could be a stepgen or PWMgen
that would definitely be cool
that could be 48 of each (actually, that probably wouldn't fit)
heh. actually, it might :)
the larger FPGA has 7.5x the number of gates, but only 6x the number of "modules" are needed (and the PWMs are smaller than the stepgens, I think)
what I think would be interesting is to put classicladder inside the fpga
yep. I'd love that too
or any small microcontroller
and possibly a lightweight CPU for ... right
the 1.5M FPGA could actually hold a pretty good size CPU, though I'm not sure there are any free/Free ones
[20:26:20] <jepler> http://www.opencores.org/browse.cgi/filter/category_microprocessor
looking ther enow :)
I know the NIOS and MicroBlaze will fit in that many gates, with some pretty good features (32-128 registers, 32-bit, cache ...)
have one CPU core for each I/O connector, something you can target with gcc but with a few choice instruction set additions that make fast encoder / pwm / step generation possible
(I should just keep my mouth shut since I'm not going to work on anything of the sort)
a 24-bit CPU should fit nicely
I have a question.. I just did a cvs update and make... Now the lathe_pluto.ini file shows this
MAX_VELOCITY = 1.66
MAX_ACCELERATION = 20
BACKLASH = 0.000
MAX_VELOCITY = 23
MAX_ACCELERATION = 500
BACKLASH = 0.06
that was a recent change? I guess I could look my self couldn't I ;)
also got an error saying that the axis_toolchange.hal didn't exist. I ended up copying the file from one of the sim configurations.
your copy must have been really old - I don't remember it being in inches
but yes I did update cvs to match what I was running at workshop
I had initially got it at the workshop. I changed it to inches.. That was my copy.