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[00:23:16] <micges-dev> PCW: I see that packet too
[00:24:54] <PCW> not sure when it snuck in maybe with the DPLL
[00:26:18] <PCW> its pretty bogus since 0 is not hostmot2 address that ever been used
[00:27:32] <micges-dev> it seems that it read 32 bits at addr 0x0, right?
[00:28:57] <Tom_itx> PCW is the 7I90 the one that's similar to the 7i43 with more IO?
[00:28:59] <PCW> Yes
[00:29:07] <PCW> and yes
[00:29:11] <Tom_itx> :)
[00:29:32] <Tom_itx> 72 opposed to 48..
[00:29:36] <Tom_itx> iirc
[00:29:45] <PCW> yes
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[00:30:15] <Tom_itx> can the first 2 plugs be mapped the same as the 7i43?
[00:30:26] <PCW> yeah
[00:30:28] <Tom_itx> so i don't have to rewire anything...
[00:31:51] <micges-dev> PCW:
http://pastebin.com/cRMbhJrm
[00:32:00] <Tom_itx> is that what jepler is using on his arm board with SPI interface?
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[00:33:21] <PCW> micges-dev: so that looks right
[00:35:55] <PCW> Tom_itx: yes AFAIK
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[00:39:26] <micges-dev> PCW:
http://pastebin.com/bddHRNGe
[00:41:00] <PCW> and that also looks OK
[00:41:47] <micges-dev> so it's not from tram
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[00:44:38] <PCW> must be a unconverted = unqueued read hiding somewhere
[00:47:28] <micges-dev> enable_raw in config string enable it
[00:48:41] <PCW> Ahh so its my fault (from before the stepgen DPLL stuff was in the driver)
[00:49:15] <PCW> so not really a serious bug at all
[00:49:20] <micges-dev> write is done with strobe but read is in every cycle so if addr is 0x0 then you got bogus packet
[00:50:28] <PCW> and default address is 0x0000
[00:50:38] <micges-dev> yep
[00:51:22] <micges-dev> not possible to add it to tram but maybe it can be done by queue_read not direct read
[00:52:25] <PCW> Well its a lot less important than I thought so pretty low priority
[00:55:31] <micges-dev> using queue_read is working, I'll add patch later
[00:55:59] <micges-dev> same for write
[00:57:28] <PCW> ok turn of raw access/ read times ~ 1/2ed :-)
[00:59:14] <PCW> Thanks!
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[13:21:37] <skunkworks__> 2 days at 2khz
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[17:24:50] <Connor> skunkworks__: 2 days at 2khz ??
[17:25:43] <skunkworks__> testing a 7i80 (Ethernet connected mesa card) running the servo loop at 2khz
[17:26:00] <Connor> Ah
[17:26:46] <skunkworks__> realtime control loop over Ethernet is just cool!
[17:30:59] <Connor> Sounds like it.
[17:31:17] <Connor> Just now converting my machine from pport to MESA 5i25 / 7i76
[17:38:43] <skunkworks__> nice
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[21:39:54] <PCW> well g3258 looks pretty decent RTAI wise ~6 usec base and ~4 usec servo running youtube flash and a bunch of glxgears
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[21:40:17] <PCW> no bios changes from default yet
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[22:43:01] <CaptHindsight> one thing that memleak spent some time on with the newer RTAI branch is getting <25uS latency for RTAI along with smooth video rendering and playback
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[22:45:22] <CaptHindsight> it looks like some video drivers access hardware directly and violate anything RTAI does to schedule threads
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[22:46:35] <CaptHindsight> I think he traced something back to X that didn't care what RTAI was doing
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[22:50:51] <PCW> The G3258 gets about 21 usec latency on preemt-RT
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[22:52:29] <PCW> and seems to run hm2_eth easily at 2.5 KHz
[22:53:38] <CaptHindsight> PCW: any launch date for the ethernet fpga boards?
[22:54:59] <PCW> they are all available now (well except 7I92) we have not been saying much until we are really sure they work well for linuxcnc
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[22:55:23] <CaptHindsight> yeah I meant the 7i92
[22:55:58] <PCW> middle of this month I hope
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