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[02:30:44] <skunkworks_> woke up this morning to the fridge not working... purchased in 09
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[02:41:39] <jepler> skunkworks_: yuck
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[02:56:42] <skunkworks_> I hope that it was just a bad fuse... (curcuit board mounted 15amp) it failed on one of the ends.. didn't open in the middle..
[02:56:54] <skunkworks_> replaced it and it is still running
[02:57:35] <skunkworks_> looks like maybe it wasn't soldered very
[02:57:40] <Tom_itx> sounds like it may have been faulty
[02:57:48] <skunkworks_> time will tell
[02:58:33] <Tom_itx> anything spoil?
[02:59:21] <Tom_itx> that can cost more than the appliance...
[03:00:16] <skunkworks_> heh - no. it must have happened close to the morning.. thought the bulb went bad - pulled the bulb and thought -'hey - the filament looks good'
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[03:01:21] <skunkworks_> so after finding the fuse that looked fine was wide open - jumped it until I could solder some pigtails on some replacement fuses..
[03:01:36] <skunkworks_> so far so good.
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[03:17:51] <skunkworks_> http://electronicsam.com/images/KandT/testing/stirling/stirling.jpg
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[05:41:39] <kwallace> I'm trying to recall an .ini entry I may have made a while back but can't seem to remember -- features = 4 and found
https://github.com/araisrobo/linuxcnc/blob/master/tests/interp/abort-hot-comment/test.ini
[05:42:28] <kwallace> Gremlin and lathes seem to come to mind, maybe -- any ideas?
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[05:55:53] <kwallace> I'll have to sleep on it, G'night.
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#linuxcnc-devel to:
http://linuxcnc.org | Latest release: 2.6.2
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[15:23:47] <cradek> seb_kuzminsky: yay! thanks again.
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[15:42:58] <seb_kuzminsky> :-)
[15:49:35] <seb_kuzminsky> the only release-manager thing i can't do is update the www.linuxcnc.org front page News section
[15:49:55] <archivist> just like London buses , you wait ages then 3 come at once.../me ducks
[15:52:32] <seb_kuzminsky> heh
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[15:53:49] <seb_kuzminsky> both the .1 and .2 bugfixes could have been found sooner if people had been testing the -pre releases... /me ducks
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[17:10:06] <jepler> pcw_home: so it looks like that first word should read back as AAAAAAAA ?
[17:10:33] <pcw_home> Yes
[17:11:15] <jepler> none of the phase and polarity flags have given me that
[17:11:30] <pcw_home> Hmm
[17:11:35] <jepler> 55 55 55 54 B5 55 AA A0 45 55 A3 00 55 55 55 54
[17:11:50] <jepler> that's what I read back with all 4 of the phase / polarity options
[17:12:03] <pcw_home> what clock rate?
[17:12:56] <jepler> supposed to be 500kHz
[17:13:57] <pcw_home> CS timing maybe
[17:14:51] <jepler> I don't seem to have any CS timing control on the linux end
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[17:15:18] <jepler> btw mode 0 and 3 give consistent values (55 55 55 54), mode 1 and 2 give varying values
[17:18:18] <pcw_home> the SPI slave interface samples input data on the clock rising edge and outputs data on the falling edge
[17:18:20] <pcw_home> (this matches CPOL,CPHA = 0,0 AFAICT)
[17:19:36] <jepler> scope shows ~3us from falling /CS to first falling edge of SCK
[17:21:09] <pcw_home> ok so plenty
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[17:22:11] <jepler> I guess I should dig out my logic analyzer, a 2-channel scope is not the right tool for this
[17:22:16] <pcw_home> so SPI master should sample its input data on rising edge of clock, but it sounds like it is not
[17:22:26] <jepler> is it right that SCK should be high at the start and end of the transaction?
[17:22:34] <pcw_home> no
[17:22:46] <pcw_home> wrong cpol
[17:23:10] <pcw_home> should idle low
[17:26:28] <jepler> hmm
[17:26:52] <jepler> both choices for clock polarity have clock being high at the falling edge of CS
[17:27:25] <pcw_home> CPOL setting is broken maybe
[17:29:54] <jepler> hmm, somewhere along the line the 7i31 blinkenlights changed from being all lit
[17:30:02] <jepler> something must have been received and acted on
[17:30:09] <jepler> not the lights pattern I intended, however
[17:32:13] <pcw_home> if the clock starts high the first falling edge will output bit 30 (bit 31 will be lost)
[17:32:41] <pcw_home> (the 0x5555554)
[17:32:53] <jepler> what happens when I change CPOL is that the first clock pulse is a runt
[17:33:04] <jepler> I can get ~~~~~~~_~~__~~__~~...
[17:33:11] <jepler> or ~~~~~~~__~~__~~__~~...
[17:34:03] <pcw_home> as long as they happen when CS is not asserted, they dont matter
[17:34:14] <jepler> oh no, this is all after CS goes low
[17:34:35] <pcw_home> oops thats just wrong
[17:35:39] <pcw_home> http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
[17:36:13] <pcw_home> maybe the driver is dwiddling with the modes dynamically
[17:36:14] <jepler> no, that's not particularly how my waveform looks
[17:36:45] <jepler> SCK is just not behaving like that
[17:36:53] <pcw_home> My guess is the driver is funky
[17:37:08] <jepler> that's not what I wanted to find out
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[17:37:50] <pcw_home> it can be worked around if need be
[17:39:01] <pcw_home> if CPOL =1 makes the clock look right the FPGAs polarities could be fixed
[17:39:34] <jepler> all the combinations I bothered to scope so far have clock being at high logic level at the start
[17:39:53] <pcw_home> weird
[17:40:05] <jepler> no sign of functional fixes to the driver ("s3c24xx") since the tree I'm working from
[17:40:29] <jepler> bbl, farmer's market time
[17:40:38] <pcw_home> Bye
[17:52:23] <CaptHindsight> doesn't take up much FPGA space and there's a SPI analyzer plugin
http://www.sump.org/projects/analyzer/client/
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[19:00:07] <jepler> CaptHindsight: actually I just brought a board with that on it upstairs
[19:00:13] <jepler> last time I used it, the software was irritating
[19:00:30] <jepler> worse, it was java
[19:01:14] <CaptHindsight> yeah, just a low budget for-what-it's-worth suggestion
[19:01:25] <jepler> sure, I appreciate it
[19:04:27] <CaptHindsight> I was thinking the VHDL could be modified to only 6-8 channels for things like this
[19:05:03] <CaptHindsight> and sit on a mesa FPGA with enough spare gates
[19:05:32] <CaptHindsight> add logic analyzer to HAL
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[19:54:19] <pcw_home> actually if the clock is high when CS is asserted (and CPOL is 0) you dont need a logic analyser
[19:54:20] <pcw_home> this needs to be fixed in the driver (or if the hardware is broken, make a SPI slave that works with CPOL=1)
[20:00:28] <jepler> so the logic analyzer sees a rather noisy version of the signals
[20:00:35] <jepler> reading on the 5V side after the TXB0401
[20:01:50] <jepler> but what I thought I had seen with the clock starting out high is not there now
[20:02:11] <jepler> .. there have been many reboots of the odroid in between, so it's possible some bad register setting will stick, rather than getting cleared
[20:03:33] <memleak> what API used by the machine plot UI? the screen where it shows the backplot / visual trace of the machine?
[20:03:41] <memleak> *is used
[20:04:07] <memleak> i.e. opengl, directfb, sdl, etc.
[20:04:20] <jepler> memleak: opengl
[20:04:34] <jepler> http://emergent.unpythonic.net/files/sandbox/ow-my-cs.png
[20:04:37] <memleak> oh nice!
[20:04:50] <jepler> I don't even know what the mesa's supposed to do with a waveform like that!
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[20:10:10] <Tom_itx> is CS active low?
[20:10:20] <jepler> Tom_itx: yes
[20:10:27] <Tom_itx> same with the data?
[20:11:22] <Tom_itx> doesn't look so odd... you should expand it to a couple transfers
[20:11:38] <Tom_itx> the saleae will give you hex data out
[20:11:38] <jepler> you don't think it's weird for CS to go high for a few ns in the middle of a transfer?
[20:11:57] <Tom_itx> i can't tell where the transfers start or stop
[20:12:01] <Tom_itx> between bytes?
[20:12:04] <jepler> one transfer is shown there
[20:12:08] <Tom_itx> it could be a bit odd yes
[20:12:55] <jepler> http://emergent.unpythonic.net/files/sandbox/ow-my-cs2.png
[20:12:59] <jepler> there it is zoomed in
[20:13:21] <Tom_itx> are they long enough to interfere?
[20:13:24] <jepler> I am pretty confident that is just noise on CS
[20:13:27] <Tom_itx> looks 'not normal'
[20:13:52] <Tom_itx> they're not very wide for sure
[20:14:16] <Tom_itx> i wonder what else is switching at those times
[20:14:24] <Tom_itx> is it coming from the fpga?
[20:14:35] <jepler> if I zoom further, almost all of the spurious pulses are at a moment when SCK has a transition
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[20:15:18] <jepler> the setup for this trace is: oduino SPI @ 1.8V -> 6" wire -> TXB0401 level translator @ 5V -> 6" wire -> open logic sniffer with its own level translation chip
[20:15:20] <Tom_itx> is CS held high and pulled low? maybe add a pulldown on it to see what happens
[20:15:27] <CaptHindsight> http://www.kerrywong.com/blog/wp-content/uploads/2013/02/SPI.png SPI (write)
[20:17:00] <jepler> Tom_itx: I don't have accurate information about the I/O details of the SPI pins, beyond that they are on a 1.8V standard
[20:17:12] <jepler> so it is possible that CS is open collector or something like that
[20:17:20] <Tom_itx> yeah
[20:17:31] <Tom_itx> i wouldn't think so but you never know
[20:17:44] <jepler> er, odroid, not oduino
[20:17:47] <jepler> so many damned devices
[20:18:05] <Tom_itx> this is on the arm device?
[20:18:16] <jepler> yes
[20:18:36] <jepler> mesa card is not even hooked up in this test
[20:18:47] <Tom_itx> ok
[20:19:41] <CaptHindsight> plus SPI has 4 modes for clock polarity and clock edge
[20:19:48] <Tom_itx> right
[20:19:55] <Tom_itx> CPOL CPHA sets that
[20:21:21] <jepler> assuming that the driver handles the various modes correctly, just trying all 4 modes didn't give a working result
[20:21:22] <pcw_home> currently CS high clears the bit count so glitches on CS are bad
[20:21:36] <pcw_home> bit count
[20:24:40] <jepler> perhaps my choice of level translator was a poor one.
[20:24:58] <jepler> it had the virtue of being on a breakout board :-/
[20:25:53] <pcw_home> you might scope CS on the 1.8V side
[20:28:51] <pcw_home> I had intended to put a digital filter on CS, that might help
[20:28:53] <pcw_home> (also make sure you have multiple grounds, dont need much ground bounce to get to a 1.8V logic high
[20:28:54] <pcw_home> maybe as little as ~0.7V
[20:31:51] <CaptHindsight> looks like all SPI signals on that board are just brought right to a header, no passives
[20:33:00] <CaptHindsight> https://doc-0s-4g-docs.googleusercontent.com/docs/securesc/ha0ro937gcuc7l7deffksulhg5h7mbp1/qbl6iul9dfn8vknsk6jp5ou0uc7v64f2/1407700800000/13129578833489239856/*/0B4UPrML8Nk9lSk5aai1MQ1VVTmc?h=16653014193614665626&e=download
[20:33:30] <jepler> pcw_home: there's only one ground on the odroid's headers
[20:34:13] <pcw_home> if you have cables, the odroid side cable should be as short as possible
[20:38:07] <jepler> going back to te scope, there's easily noise seen on the 1.8V side's CS line that exceeds 750mv
[20:39:49] <pcw_home> well, thats not good...
[20:40:41] <pcw_home> scope ground on odroid ground pin?
[20:40:55] <jepler> no, which I was just about to fess up to
[20:46:56] <CaptHindsight> from the schematic it's just the 4 SPI pins on the 4 pin header
[20:47:14] <jepler> CaptHindsight: yes, so the nearest ground I can take is on the next header, an inch or two away
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[20:50:38] <jepler> measuring at the end of the 6" wires, there's still noise >700mV
[20:51:11] <jepler> I guess 1.8V logic is not intended to run very far in unshielded wire
[20:52:58] <jepler> OK, spi from this board goes on the back burner now
[20:53:10] <jepler> I'll actually make some heady working on an assembler preprocessor.
[20:54:41] <CaptHindsight> yeah, don't worry about it. I'll take a look at SPI again here as soon as I get a chance
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[20:56:31] <jepler> there are too many untested parts in my SPI setup. odroid, level translator breakout, and spi on 7i43 are all potential sources of egregious brokenness
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[21:03:44] <jepler> https://github.com/rumpkernel/wiki/wiki
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[21:08:36] <CaptHindsight> memleak has the cubie2 running again
[21:09:02] <CaptHindsight> and all the tools are here
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[21:23:10] <CaptHindsight> preempt_rt on new AMD APU's with the hardware accell driver jumps to 240uS under abuse, so we are stuck until AMD fixes the driver
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[22:13:01] <Tom_itx> jepler i've had good luck with NXP level translators
[22:13:20] <Tom_itx> work down to 1v
[22:13:32] <Tom_itx> no direction pin necessary
[22:15:06] <Tom_itx> GTL2003PW is an 8bit wide ver, they vary from 2 bit to many
[22:18:47] <Tom_itx> i could show a layout for it if you're interested
[22:44:25] <CaptHindsight> SPI kernel driver Master Mode Only for the A20
https://github.com/linux-sunxi/linux-sunxi/blob/sunxi-3.4/drivers/spi/spi_sunxi.c
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