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[00:28:14] <PCW> migces: hi
[00:29:30] <micges> PCW: hi
[00:32:30] <PCW> 7I92 works so will need mMF and linuxcnc collateral
[00:32:46] <PCW> bbl SO yelling
[00:33:12] <micges> ok
[00:34:03] <PCW> ethernet 34 I/O P2 = IO 0..16 P1 = I/O 17..33
[00:34:25] <PCW> (ethernet 5i25 basically)
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[12:47:42] <jepler> seb_kuzminsky: yes, I vaguely recall this...
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[12:59:12] <jepler> seb_kuzminsky: I wonder if this from dmesg is relevant [7629351.374551] ldpreload_main[1711]: segfault at 18 ip 00007f1fcb5fcc09 sp 00007fffc73f9b10 error 4 in libstdc++.so.6.0.13[7f1fcb533000+f6000]
[13:00:14] <jepler> oh maybe that's just the configure test for libgl buggerupness
[13:00:50] <jepler> ./ldpreload_main >/dev/null 2>&1
[13:00:52] <jepler> nevermind
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[13:22:27] <jepler> seb_kuzminsky: to be honest I don't even know what that test is testing
[13:22:44] <jepler> "bug 357"
[13:23:48] <jepler> .. a crash
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[13:23:54] <jepler> which could have been mah's fix or could have been my fix
[13:25:27] <jepler> seb_kuzminsky: from the buildbot log, it sure does look a lot like the test proceeded as intended but the timeout was too short
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[15:18:16] <seb_kuzminsky> jepler: i think that's what it is, i extended the timeout and will keep an eye on it
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[15:25:48] <KGB-linuxcnc> 03Sebastian Kuzminsky 052.6 8f3db8e 06linuxcnc 10VERSION 10debian/changelog update changelog & VERSION for 2.6.2 * 14http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=8f3db8e
[15:25:49] <KGB-linuxcnc> 03Sebastian Kuzminsky 05signed tags af36c2c 06linuxcnc 03v2.6.2 LinuxCNC v2.6.2 (tagged commit: 8f3db8e) * 14http://git.linuxcnc.org/?p=linuxcnc.git;a=commitdiff;h=af36c2c
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[17:47:16] <jepler> [ 0.000000] NR_IRQS:549
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[18:15:50] <jepler> pcw_home: with TXB0104 level translator, I've looped MOSI -> MISO and tested for reception at various rates. Vcca=1.8 Vccb=5.0. At 50MHz, messages are reliably echoed; by 75MHz, they aren't.
[18:16:17] <jepler> e.g., at 60MHz
[18:16:18] <jepler> 60
[18:16:18] <jepler> > 55aa f00f
[18:16:18] <jepler> < 55aa f00f
[18:16:32] <jepler> but by 75MHz
[18:16:32] <jepler> > 55aa f00f
[18:16:32] <jepler> < 2ad5 f807
[18:17:30] <jepler> (loop is on 5v side, exynos spi module is driving 1.8v side)
[18:20:12] <pcw_home> So thats probably mostly the delay contributed by the translator (did you try pokeing at the sample delay settings?)
[18:20:30] <jepler> no. I read the kernel enough that I believe it's initialized to 0
[18:22:59] <pcw_home> well if it translates it should work at _some_ frequency, tweaks or not
[18:23:29] <jepler> pcw_home: the toplevel that is needed for spi communicaton with hostmot2 is called what?
[18:23:50] <pcw_home> TopGCSPIHostMot2
[18:24:05] <jepler> OK
[18:25:33] <pcw_home> (GC=GlobalClock)
[18:25:34] <pcw_home> I have a AC version but not done yet (SPI clock is just another data input sampled at 200 MHz clockhigh)
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[18:42:36] <pcw_home> There will be some issues making the TopGCSPIHostmot2 work with a 7I43 (since it was really only written for the 7I90 = SP6)
[18:42:37] <pcw_home> at the minimum the clocks (clockhigh,clocklow, clockmed) need to be lowered for the 7I43
[18:43:37] <pcw_home> (maybe, check if it meets timing)
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[18:50:35] <jepler> still doing battle with the hostmot2-firmwares build system, nowhere close to checking timings :-/
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[18:53:39] <pcw_home> I would cheat and use a project file :-)
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[18:54:27] <pcw_home> need to do battle with some weeds
[18:54:28] <pcw_home> biab
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[19:24:04] <jepler> > WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
[19:24:07] <jepler> your design.
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[19:25:00] <jepler> the failing constraint is said to be TS_clkfx0 = PERIOD TIMEGRP "clkfx0" TS_CLK / 4 HIGH 50%
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[19:50:44] <jepler> micges or pcw: I set my 7i43 with W4 down and W5 up, which should give me "USB Config". but mesaflash just hangs after writing octal 0377 to /dev/ttyUSB1
[19:51:00] <jepler> PWR: lit DONE: lit INIT: dark
[19:51:10] <jepler> what should I do next to troubleshoot?
[19:52:50] <CaptHindsight> is the installer broken on wheezy net ISO? Just tried it and after login the taskbar disappears and all that left is the desktop background
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[19:55:29] <jepler> CaptHindsight: choosing an "install" option from the bootloader screen?
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[19:59:43] <CaptHindsight> heh, I get the "Oh No" screen after a few minutes, can recover
[19:59:52] <CaptHindsight> can/can't
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[20:00:50] <CaptHindsight> jepler: this is after the net install (1+ hour of downloads and installing of packages)
[20:01:56] <jepler> oh you're not talking about linuxcnc.org's binary.hybrid.iso, but about a debian.org iso?
[20:02:02] <jepler> I would be surprised if it were that broken
[20:02:58] <CaptHindsight> yeah, debian net ISO from debian.org, wanted to try it before adding Linuxcnc
[20:03:50] <jepler> OK, after power-cycling the card, mesaflash does detect it
[20:03:50] <jepler> $ ./mesaflash --device 7i43 --usb --addr /dev/ttyUSB1
[20:03:50] <jepler> USB device 7I43 at /dev/ttyUSB1
[20:04:49] <jepler> ERROR: Board 7I43 doesn't support FPGA resetting.
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[20:15:04] <pcw_home> umm, you probably have to load a usb compatible config first
[20:16:05] <pcw_home> kind of a bootstrap operation...
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[20:17:18] <jepler> pcw_home: hmm
[20:17:18] <jepler> [ 2164.352558] spidev spi1.0: I/O Error: rx-0 tx-1 res:rx-p tx-f len-4
[20:17:22] <jepler> uh oh, I made spi grumpy
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[20:19:58] <jepler> pcw_home: after commenting out the reset in mesaflash, I can use --program with my bitfile
[20:20:06] <jepler> .. the DONE and INIT lights both go out, though mesaflash hangs
[20:20:57] <jepler> but in any case the firmware's not right. spi reads back gibberish
[20:21:23] <jepler> > 040ca860 00000000 00000000 00000000 00000000 00000000 00000000
[20:21:23] <jepler> < xxxxxxxx ff7ba86f fdfffffd ffffedff ffffffff fffffdff fffffffe
[20:25:48] <jepler> oh well, out of time for today
[20:26:45] <pcw_home> yeah its not likely to be right the first time
[20:31:26] <pcw_home> also maybe clock polarity and clock phasing (CPOL and CPHA)
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[20:37:55] <jepler> it's possible it's that simple, or that I messed up my wiring
[20:38:23] <jepler> more likely that I've failed to properly adapt the spi firmware, which puts me well out of my depth
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[20:43:45] <pcw_home> The SPI interface echos 0xAAAAAAAA on commands so that should be a a good minimal test
[20:44:36] <pcw_home> heck if you really want to mess with this I should send you a 7I90
[20:45:28] <pcw_home> so you are not trying to debug too many things at once
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[20:50:21] <jepler> once again, I wouldn't say "no"
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[20:50:58] <jepler> but this is way out further in left field than "I want to work on finishing hm2-eth"
[20:51:49] <jepler> (oh by the way, I was using mesaflash on arm to do the above usb talking)
[20:55:08] <pcw_home> The USB is serial port emulation so should run on most anything
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[20:57:57] <pcw_home> What XXXXXXXX reads may be a clue to whats going wrong
[20:58:48] <pcw_home> (it may also be that you are not meeting timing so all data is funky)
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[21:07:47] <jepler> > 040ca860 00000000 00000000 00000000 00000000 00000000 00000000
[21:07:47] <jepler> < ffffffff ffffffff ffffffff ffffffff ffffffff ffffff7f dbfddfff
[21:07:51] <jepler> I think it's just not talking spi
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[21:08:40] <jepler> really gone this time
[21:08:48] <pcw_home> bye
[21:08:57] <jepler> pcw_home: thanks for the suggestions .. I think tomorrow I'll go back to assembler macros
[21:09:17] <pcw_home> do you have a active low CS?
[21:11:15] <jepler> yes
[21:11:34] <jepler> and I tried several but by no means all pha/pol options
[21:12:13] <pcw_home> even then I would not expect 0xFFFFFFFF
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[21:14:38] <jepler> NET "COM_SPICLK" LOC = "p127" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
[21:15:08] <jepler> what is COM_SPICLK vs SPICLK?
[21:15:15] <jepler> NET "SPICLK" LOC = "p70" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
[21:15:18] <jepler> the former is the one I added..
[21:15:59] <pcw_home> this is 7i43.ucf?
[21:16:02] <jepler> modified from
[21:17:06] <pcw_home> the one thats there is for the flash memory (so is an output)
[21:17:07] <pcw_home> your new won should be an input (so n o drive or slew options)
[21:17:19] <pcw_home> new one
[21:17:32] <jepler> same for CS and IN then I guess
[21:17:44] <pcw_home> yep
[21:17:50] <jepler> I guess I should have read the other ucf
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[21:18:41] <jepler> NET "COM_SPICLK" LOC ="P55" | IOSTANDARD = LVTTL;
[21:18:41] <jepler> NET "COM_SPIIN" LOC ="P56" | IOSTANDARD = LVTTL;
[21:18:41] <jepler> NET "COM_SPIOUT" LOC ="P57" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = FAST ;
[21:18:44] <jepler> NET "COM_SPICS" LOC ="P58" | IOSTANDARD = LVTTL;
[21:19:23] <pcw_home> Are you sure your ucf file is associated with the top level file?
[21:20:01] <jepler> yes, because I had errors that I resolved by editing it
[21:20:16] <pcw_home> also the 7I43 needs the funny config options mentioned in the manual (assert done last)
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[21:22:50] <jepler> hm actually I got that wrong
[21:23:01] <jepler> I thought the build system would carry it over, but it's predicated on the board being an "epp"
[21:23:39] <pcw_home> if thats not done the configuration will not finish
[21:24:07] <pcw_home> but your not supposed to be fussing with this anymore :-)
[21:25:13] <jepler> > 040ca860 00000000 00000000 00000000 00000000 00000000 00000000
[21:25:13] <jepler> < 55555554 00000000 00000000 00000000 00000000 00000000 00000000
[21:25:25] <jepler> well something is different
[21:25:43] <jepler> really, *really* going this time
[21:26:13] <pcw_home> ahh looks close, bbl
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