#emc-devel | Logs for 2010-03-04

[04:04:27] <jepler> hm, does the FPGA on the 5i20 get warm running a normal hostmot2 firmware? It's a bit toasty with my RNG firmware; having 480 ring oscillators each running at a few hundred MHz is probably a much higher power application..
[04:04:45] <cradek> I've never poked it
[04:14:54] <jepler> 'night all
[13:30:02] <ries> jepler: Just read your post on : Emc-gcode throughput Are there any open source programs that can optmize the g-code so that small line segments can get converted to arcs?
[13:33:24] <jepler> not that I know of, but that would be very cool.
[13:33:37] <jepler> ugh, should go to work. bbl
[14:51:14] <CIA-2> EMC: 03seb 07v2.4_branch * rc6b83f385d00 10/configs/hm2-stepper/hm2-stepper.hal: Don't reference gpios that dont exist on the 7i43
[14:54:01] <jepler> seb_kuzminsky: does the 9030 have any tricks to speed up reads? I only get about 4MB/s from a userspace program running at 100% CPU..
[14:54:43] <jepler> (looks like about 1 32-bit transfer per us)
[14:55:18] <jepler> http://pastebin.ca/1822651
[14:55:38] <SWPadnos> what chipset on that motherboard?
[14:56:49] <jepler> K8M800 / VT8237
[14:56:54] <SWPadnos> hmm
[14:57:20] <jepler> it's a 5 year old system, PCI+AGP
[14:57:29] <SWPadnos> I had what I consider to be a speed problem with the Intel ICH7 chipset, even when reading in a kernel module
[14:57:37] <SWPadnos> maybe 3 reads per microsecond
[14:57:48] <jepler> hm
[14:58:04] <SWPadnos> that chipset has no read combining whatsoever
[14:58:25] <SWPadnos> oh, and that was reading consecutive addresses, not a single address many times
[14:58:54] <SWPadnos> I'd expect the single address read to be worse, since it's necessary to do a complete PCI transaction for each read
[14:59:00] <jepler> hm
[14:59:22] <jepler> I think my random numbers are mapped at every location in the 0x0fxx page, so I could try sequential reads
[14:59:25] <SWPadnos> (well, it's guaranteed to be the worst case, since there is no chance of combining reads)
[14:59:33] <SWPadnos> that would be interesting
[15:03:09] <pcw_home> jepler: if you enable read-ahead and do burst reads you can get about 3-4x improvement with most MBs with the 5I20
[15:03:55] <SWPadnos> does that work on multiple reads from the same address?
[15:03:56] <jepler> how do I enable readahead? some register on the pci bridge to set?
[15:05:19] <pcw_home> SWPadnos: no must be sequential incrementing doublewords
[15:05:21] <pcw_home> jepler yes a couple of bits here and there
[15:07:26] <jepler> OK, I have PCI 9030 Data Book, I'll see if I can't find it
[15:08:03] <pcw_home> I can dig out my test code later if you want it
[15:08:05] <pcw_home> Also you can jumper the 5I20 for 50 MHz local bus, that will help a little
[15:08:07] <pcw_home> but may be fun meeting timing
[15:08:51] <pcw_home> For speed with PCI you really want DMA
[15:12:35] <pcw_home> With 5I22/5I23 I can get around 85 MB/second with DMA
[15:12:37] <pcw_home> 3X20 somewhat faster as its local PCI bus runs at 66 MHz
[15:12:38] <pcw_home> coming PCIE cards much faster
[15:13:51] <jepler> 5i20 can't dma, right?
[15:14:04] <pcw_home> Nope, target only
[15:15:45] <jepler> is it the "prefetchable" bit of the LASxRR that I want to set?
[15:17:04] <pcw_home> I vaguely remember "read-ahead" and "burst size"
[15:17:26] <pcw_home> prefetchable may be right as well
[15:17:32] <jepler> LASxBRD has burst enable, prefetch count, prefetch counter enable
[15:18:03] <pcw_home> sounds right
[15:18:59] <pcw_home> watch out for read-side effects if you have pre-fetch on
[15:19:01] <pcw_home> (FIFOs and such)
[15:36:21] <jepler> I went from 4MB/s to 5MB/s by using bus space 5 instead of 4
[15:40:52] <pcw_home> I think the best I've gotten on burst reads is like 14 MB/s
[15:40:53] <pcw_home> We've had customers that got around 20 MB/s with max tweaks
[15:40:55] <pcw_home> but they've all moved on to DMA capable cards
[15:41:02] <jepler> but sequential reads and the LASxBRD register twiddling didn't make any further difference
[15:43:44] <jepler> LAS3BRD and bus space 5 correspond, right?
[15:47:14] <pcw_home> Been years since I looked at this, let me see if I can find what I did...
[15:54:26] <pcw_home> 1. enable burst (bit 0 = 1)
[15:54:28] <pcw_home> 2. set read-ahead size to 4 lwords (bits 5,4,3 = 101)
[15:54:29] <pcw_home> Also wrote CNTRL reg to enable read-ahead (bit 16 = 1)
[15:59:59] <jepler> I also set bit 14, PCI r2.2 features enable
[16:00:02] <jepler> that got me to 8MB/s
[16:12:14] <jepler> prefetch of 4 vs 16 doesn't make a difference
[16:14:06] <jepler> I take it back, 7MB for prefetch 4, 8MB for prefetch 16
[16:24:34] <pcw_home> Some of it may be CPU chipset related as well
[16:31:49] <jepler> there's no specific rate I need to reach, so I think I'll call the 2x speedup a success and move on
[16:39:11] <micges> jepler:will you apply my latest patch for m67?
[16:50:14] <jepler> did you revise it since http://www.pastebin.ca/1820103 ? At a minimum you should fix the wrong comment in command.c and error handling in tpClear.
[16:51:10] <micges> ok I'll do it
[16:54:14] <jepler> also you should never use pastebins for patches, since even the "raw" view turns the file into DOS mode and makes the patch not apply.
[16:54:56] <jepler> I recently learned this the hard way myself :-/
[16:55:41] <micges> ok thanks
[17:02:31] <jepler> what is the syntax of m67?
[17:03:25] <micges> m67 E analog index Q value
[17:05:40] <jepler> OK
[17:08:04] <jepler> results of a little test look OK. Velocity is maintained while changing an output, and multiple outputs will change at the same time
[17:08:22] <jepler> the change is a little early; I assume that's due to the output change taking place at the start of the blend
[17:09:14] <micges> yes it's not perfect
[17:11:44] <micges> and for blending, have you thinking about extending blending code to test more than two vectors ahead? compared to other cnc systems emc is still very slow in G64 Pn mode
[17:11:59] <cradek> various things happen in the middle of the blend - you could put it there.
[17:12:09] <cradek> I mean there's already a test for it and a block of code that runs at that time
[17:12:28] <cradek> micges: of course, many people have *thought* about doing that
[17:13:00] <jepler> I recognize that there are users who would benefit from a more sophisticated motion planner
[17:13:13] <jepler> I don't have any plans to work on it myself
[17:13:19] <cradek> same here
[17:13:52] <cradek> I might even see some benefit from jerk limiting on my heavy machine (different issue, but same in that many people have *thought* about doing it)
[17:20:03] <micges> I understand
[17:20:50] <cradek> if you feel like working on either, please do, I'd also be happy to see a better planner
[17:21:48] <micges> I've measured that gcode programs from cam runs 2 times slower on emc than on haas
[17:22:13] <micges> this is retrofit criteria for many of my friends :|
[17:25:35] <cradek> with appropriate G64P setting?
[17:25:47] <cradek> and correct acceleration settings etc?
[17:26:28] <micges> same settings
[17:49:03] <CIA-2> EMC: 03seb 07master * r00e0c9ee3b6d 10/src/hal/drivers/mesa-hostmot2/doc/regmap: revive the firmware/driver interface documentation
[17:49:03] <CIA-2> EMC: 03seb 07master * rc6b83f385d00 10/configs/hm2-stepper/hm2-stepper.hal: Don't reference gpios that dont exist on the 7i43
[17:49:04] <CIA-2> EMC: 03seb 07master * r9196a589d396 10/configs/hm2-stepper/hm2-stepper.hal: Merge branch 'v2.4_branch'
[22:21:19] <alex_joni> wheee...
[22:21:37] <alex_joni> seems launchpad decided to restart the vcs import of emc2 git master
[22:21:48] <alex_joni> so I just got an email for each commit since 2009.04
[22:23:23] <alex_joni> revistions 7193..7593
[22:26:37] <jepler> alex_joni: lucky you!
[22:29:00] <alex_joni> yeah, very
[22:29:18] <alex_joni> at least I have imap access, so I could just delete them all
[23:11:58] <mozmck> so you're putting emc2 on laundpad? in bzr?
[23:15:58] <alex_joni> mozmck: not very actively
[23:16:09] <alex_joni> I set up an import in 2009 iirc
[23:16:19] <alex_joni> for some reason it failed after a while
[23:16:25] <alex_joni> now they started it back up
[23:16:28] <mozmck> oh. I see.
[23:16:31] <alex_joni> beats me why :D
[23:16:44] <alex_joni> it was mostly to have the name registered at launchpad
[23:16:50] <mozmck> does it keep importing changes?
[23:16:54] <alex_joni> if we ever get fed up with sourceforge
[23:17:01] <alex_joni> yeah, it should
[23:17:34] <mozmck> I just got the karmic kernel from git compiled the "proper" ubuntu way. Getting the hang of it better now.
[23:17:45] <mozmck> with rtai patch that is.
[23:18:16] <alex_joni> cool
[23:19:30] <mozmck> had problems at first, now I'm going back and creating an "rtai" flavour
[23:20:35] <alex_joni> http://bazaar.launchpad.net/~vcs-imports/emc/master/files
[23:23:17] <mozmck> neat. so that is in bzr I guess
[23:23:34] <mozmck> yep, it says right there.
[23:23:52] <alex_joni> yeah, lp keeps it in bzr
[23:24:06] <alex_joni> <- off to bed
[23:24:11] <alex_joni> good night all
[23:24:46] <mozmck> good night.
[23:25:05] <alex_joni> nice catch on the dump stuff