#emc-devel | Logs for 2007-09-13

[02:16:00] <jmkasunich> SWPadnos: I can find it pretty easily (I think)
[02:16:30] <jmkasunich> found it
[02:19:36] <SWPadnos> oh - thanks. I thikn I decided to sidestep the question for now :)
[02:19:56] <jmkasunich> I thought something like that might happen - 2+ hours is a bit long to wait
[02:20:06] <SWPadnos> I'm working on the A/D SPI block, and I wanted to parameterize the number of input/output channels
[02:20:36] <SWPadnos> which means you need to parameterize the number of registers, each of which is a bit vector, adn I wasn't sure how to do that
[02:20:51] <SWPadnos> eh - no biggie. it's probably easier this way anyway :)
[02:22:20] <SWPadnos> I wanted something like:
[02:22:22] <SWPadnos> entry multiSPI is
[02:22:24] <SWPadnos> generic (
[02:22:24] <SWPadnos> buswidth : integer := 32
[02:22:27] <SWPadnos> inchannels : integer := 3
[02:22:28] <SWPadnos> ochannels : integer :=0
[02:22:30] <SWPadnos> )
[02:22:57] <SWPadnos> with different numbers of in and out channels for the DAC (2+2), normal SPI (1+1), etc.
[02:23:45] <jmkasunich> I just looked at the section where they introduce generics and parameterized components
[02:23:55] <jmkasunich> but they don't show variable numbers of vectors
[02:24:00] <SWPadnos> heh -ok :)
[02:24:00] <jmkasunich> just variable size vectors
[02:24:43] <jmkasunich> (I've found the web to be more effective when looking for something specific, the book was more usefull when first learning about a concept
[02:25:29] <SWPadnos> I wonder if it's possible to make this:
[02:25:30] <SWPadnos> ibus : in std_logic_vector(buswidth-1 downto 0);
[02:25:32] <SWPadnos> into this:
[02:25:34] <SWPadnos> ibus(inchannels-1 downto 0)) : in std_logic_vector(buswidth-1 downto 0);
[02:25:39] <SWPadnos> err - minus 1 paren
[02:25:45] <jmkasunich> probably
[02:25:56] <jmkasunich> I don't recall if array syntax is [] or ()
[02:26:12] <jmkasunich> but I think "array of vectors" might be what you want
[02:26:33] <SWPadnos> well, I want to have individual select bits so any of the registers can be read
[02:26:48] <SWPadnos> hmmm
[02:28:43] <SWPadnos> but then there needs to be special handling of "0"
[02:28:53] <SWPadnos> 0-1 downto 0 probably isn't a great thing
[02:29:15] <jmkasunich> you don't really need zero channels
[02:29:29] <jmkasunich> 1-1 downto 0 is the real minimum
[02:29:40] <SWPadnos> right, that's the problem
[02:29:51] <SWPadnos> I do want to allow for input-only or output-only
[02:29:54] <jmkasunich> but that might still make it barf, ISTR that a single bit vector was treated different
[02:30:00] <SWPadnos> s/do/would/ :)
[02:30:05] <jmkasunich> ah
[02:30:20] <jmkasunich> I don't recall if there is the equivalent of ifdef
[02:30:45] <SWPadnos> I suspect there is, but since I know only the VHDL I see from examples ...
[02:36:27] <jmkasunich> I wonder if a generate loop can work with 0 iterations
[02:36:46] <jmkasunich> for n in 0 to regs-1 generate
[02:36:48] <jmkasunich> somestuff
[02:36:52] <jmkasunich> end generate;
[02:37:00] <SWPadnos> can you use generate in an entity definition?
[02:37:08] <jmkasunich> I dunno
[02:37:58] <jmkasunich> I was thinking in terms of defining a single channel entity and then generating however many you need, rather than trying to define a variable size entity
[02:38:16] <SWPadnos> ah - that's another approach I had considered
[02:38:26] <SWPadnos> I'd need stacked generators though
[02:38:34] <SWPadnos> actually, I need that anyway
[02:38:41] <SWPadnos> nested - not stacked
[02:39:01] <SWPadnos> I need 2 separate interfaces, each with 3 input channels
[02:39:50] <SWPadnos> then there are 2 interfaces, each of which goes to 2 DACs, which share one input (I think), but have two outputs (I/O from the FPGA perspective)
[02:40:09] <jmkasunich> you can nest generate statements
[02:40:39] <SWPadnos> ok, that's a good thing. so if I can figure out how to put stuff together at the higher level, I can use lower level blocks
[02:40:47] <jmkasunich> yeah
[02:41:22] <SWPadnos> the good news is that I have extra time to do this, because the stupid assembly house can't find some of my parts
[02:41:40] <SWPadnos> you know, the ones I had fed-exed to them for Monday delivery
[02:41:40] <jmkasunich> thats only semi-good
[02:41:45] <SWPadnos> yeah - tell me about it
[02:41:50] <jmkasunich> good is when the customer moves the schedule out
[02:42:10] <SWPadnos> well, that happened as well, so that is a good thing
[02:42:33] <SWPadnos> it was supposed to be demonstrated to the end customer next Monday, but I think it's put off until the 24th
[02:42:46] <SWPadnos> I wish it were put off until October 24 ;)
[02:54:42] <SWPadnos> holy crap. I'm looking at a sort of VHDL web tutorial, and the company is jus tabout next door to me
[02:54:53] <jmkasunich> handy
[02:55:21] <SWPadnos> yeah. I may even know the guy
[02:55:31] <SWPadnos> http://gmvhdl.com/
[03:00:10] <tomp> they have a free HC11 core, so you can do embedded forth, lucky guy ;)
[03:00:16] <SWPadnos> luvvvly
[03:00:18] <SWPadnos> not!
[03:00:37] <SWPadnos> there was forth for the 6502 as well
[03:04:42] <jmkasunich> sleepy... goodnight
[03:04:52] <SWPadnos> night. thanks for the VHDL talk
[19:20:28] <cradek> it's apparent that nobody uses block delete...
[19:21:00] <SWPadnos> heh
[19:21:18] <SWPadnos> or perhaps it should have been called "program abort"
[19:21:37] <SWPadnos> or was it "optional program abort"? :)
[19:21:48] <cradek> hmm maybe so
[22:34:21] <jmkasunich_> jmkasunich_ is now known as jmkasunich