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[01:34:17] <SWPadnos> jmkasunich: are you around?
[01:34:55] <jmkasunich> maybe
[01:34:58] <SWPadnos> heh
[01:35:10] <SWPadnos> nothing high level or philosophical, I promise ;)
[01:35:42] <SWPadnos> actually, I'm looking for a HAL solution, and the only ones I can come up with are complex
[01:35:52] <jmkasunich> ok
[01:36:08] <SWPadnos> I was wondering if (a) you had any better ideas or (b) you could help a little with design of a new component
[01:36:22] <jmkasunich> what are you trying to do?
[01:36:59] <SWPadnos> if you read about 30 lines back, I describe "the new checkresult" and trying to check timing of quadrature (or any other) steps
[01:37:36] <jmkasunich> so you want to measure the time between pulses or edges
[01:37:52] <SWPadnos> yep
[01:38:10] <SWPadnos> in HAL, it would be counting the number of thread runs during which the inputs remain the same
[01:38:35] <SWPadnos> which is a PITA with mathc8 and a bunch of muxes / flipflops
[01:38:52] <jmkasunich> you could use the integrator, with the step signal connected to reset
[01:39:21] <SWPadnos> hmmm
[01:40:12] <SWPadnos> generating a reset for a quadrature stepgen output isn't simple
[01:40:26] <SWPadnos> you still need latches for the old phase-* outputs
[01:40:36] <SWPadnos> but that's a good thought
[01:41:00] <jmkasunich> "edge" would work
[01:41:10] <SWPadnos> true
[01:41:28] <SWPadnos> well, two edges and an or
[01:41:34] <jmkasunich> yeah
[01:41:46] <SWPadnos> ok. maybe I'll mess with that. thanks
[01:41:54] <jmkasunich> sure
[01:42:00] <SWPadnos> I knew I just wasn't seeing something obvious :)
[01:55:10] <SWPadnos> crap - need 4 edges, there's no "either" option
[03:53:14] <jmkasunich> hi matt
[03:53:25] <mshaver> hey john
[03:53:26] <jmkasunich> I'm about to reply to your mail
[03:53:30] <mshaver> good
[03:53:49] <jmkasunich> that "megacore" license is almost certainly completly irrelevant
[03:53:59] <mshaver> how so
[03:54:16] <jmkasunich> megacores are predesigned chunks of IP, such as a cpu or a bus interface or what have you
[03:54:24] <jmkasunich> that you license, and then embed in your FPGA design
[03:54:30] <jmkasunich> Jeff used no such things
[03:54:46] <jmkasunich> just plain old verilog code
[03:55:16] <jmkasunich> (code that _he_ created, and holds copyright to)
[03:55:38] <mshaver> but he used their tool, which spit out code like in <looking up the file name>
[03:56:49] <mshaver> pluto_servo.qsf
[03:58:20] <jmkasunich> its a user constraint file.... whats the big deal?
[03:59:45] <mshaver> it contains terms like "ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON" which could be construed as "direct product thereof" in paragraph 10.2" in
[04:00:17] <mshaver> ...the agreement.
[04:00:30] <jmkasunich> which one? the megacore one?
[04:00:37] <mshaver> yes
[04:00:46] <mshaver> I know it's bullcrap
[04:00:59] <mshaver> , but it's complex legal bullcrap
[04:01:07] <jmkasunich> "the megacore function"
[04:01:14] <mshaver> yes
[04:01:19] <jmkasunich> he did NOT use any megacore functions!!!!
[04:02:59] <mshaver> Ok, but doesn't a megacore function include any output from Quartus?
[04:03:19] <jmkasunich> no
[04:04:05] <mshaver> It is a "one or more design files", they don't specify whether the files in question are provided by Altera, or are user generated.
[04:05:15] <jmkasunich> when people in the FPGA business talk about "cores", they are talking about predesigned functions
[04:05:19] <jmkasunich> like this:
[04:05:20] <jmkasunich> http://www.altera.com/products/ip/design/ipm-design.html
[04:06:19] <mshaver> John, I do understand your point, and from an engineering perspective I do agree with you completely.
[04:06:36] <jmkasunich> put "megacore" into the search box at altera, and you get docs for PCI-express bus interfaces, FFT blocks, SDRAM controllers, etc
[04:07:02] <jmkasunich> he did not use any of that IP stuff, so the "megacore" license is completely irrelevant
[04:07:23] <mshaver> It's just that this license won't be interpreted by engineers, it will be interpreted by lawyers.
[04:07:24] <jmkasunich> this is NOT just an engineering perspective - its also the legal one
[04:07:44] <jmkasunich> its the WRONG license
[04:07:51] <jmkasunich> its not a matter of interpreting it
[04:08:42] <jmkasunich> thats like saying a windoze user who doesn't have office is subject to the terms of the office license as well as the main windows license
[04:09:09] <mshaver> OK, I guess I'm just really leery of outfits that have lots of strings attached.
[04:09:19] <jmkasunich> I can agree with that
[04:09:28] <jmkasunich> but please don't make the FUD worse
[04:09:33] <mshaver> I also can't see what damages Altera could possibly claim.
[04:09:52] <jmkasunich> gene doesn't know wtf he is talking about
[04:09:56] <jmkasunich> nor does paul
[04:10:02] <mshaver> But common sense and the law are often only loosly related.
[04:10:38] <jmkasunich> more info about megacores:
http://www.altera.com/products/ip/altera/mega.html
[04:10:49] <jmkasunich> they are a completely differnt product from the basic design softward
[04:10:57] <mshaver> I did consult all the referenced docs trying to find where it said, "you can distribute any files you create".
[04:11:15] <mshaver> Why in the world does their tool put that text at the top?
[04:11:25] <jmkasunich> if the design software is equivalent to a compiler, then the megacores are equivalent to a proprietary library
[04:12:18] <jmkasunich> because it was designed by greedy people
[04:12:26] <jmkasunich> you can create a constriant file manually, or you can use their editor
[04:12:36] <jmkasunich> if you use their editor, it shits in your file
[04:12:56] <mshaver> The problem with these licenses, and Rabbit's is even worse, is that they are not sufficiently explicit <what you just said>.
[04:14:17] <mshaver> I'm just so tired of this sniping about licenses. It sucks up a lot of time.
[04:14:26] <jmkasunich> we need to be very sure that what we say on the users list doesn't just play into Paul's hands
[04:15:01] <jmkasunich> the reason the old version has the altera crap in it and the new one doesn't is that jepler decrapped it after paul's first message
[04:15:16] <jmkasunich> (earlier today)
[04:16:12] <jmkasunich> here is the commit message: "take care never to edit these files in quartus; it will add erroneous Altera copyright blocks to the file"
[04:16:49] <mshaver> I read that.
[04:17:54] <mshaver> I guess that the explanation that you've given needs to be posted.
[04:18:00] <jmkasunich> I intend to
[04:18:39] <mshaver> In great detail so that it is clear to any idiot, or even a lawyer, who owns which rights to what.
[04:18:44] <jmkasunich> unfortunately we need to address the damned fud point-by-point to demonstrate that it is 99% bullshit
[04:19:04] <mshaver> That was my original intent.
[04:20:20] <mshaver> It's just that if they say, "this is subject to that license", I figured that they meant it. I figured that the pld contained some Altera provided IP.
[04:20:56] <jmkasunich> "subject
[04:20:57] <jmkasunich> # to the terms and conditions of the Altera Program License
[04:20:57] <jmkasunich> # Subscription Agreement, Altera MegaCore Function License
[04:20:57] <jmkasunich> # Agreement, or other applicable license agreement"
[04:21:14] <jmkasunich> applicable is the key word
[04:21:29] <jmkasunich> megacore licenses are not applicable, because he didn't use megacores
[04:21:43] <jmkasunich> note OR, not AND in that sentence
[04:22:12] <jmkasunich> in the beginning, they talk about"
[04:22:22] <jmkasunich> our use of Altera Corporation's design tools, logic functions
[04:22:22] <jmkasunich> # and other software and tools, and its AMPP partner logic
[04:22:22] <jmkasunich> # functions,
[04:22:39] <jmkasunich> that is a laundry list of things that he MIGHT have used
[04:23:16] <jmkasunich> he certainly did not use AMPP partner logic functions (that is third-party IP stuff - non Altera "megacores")
[04:23:55] <jmkasunich> "logic functions" probalby means megacores, although its possible that it means things like "3 input and gate" which might be part of the basic design tools
[04:25:14] <mshaver> OK, so he didn't use any of the Megacore functions. Is it OK to redistribute that constraint file or other infrastructure stuff from the design tool?
[04:25:24] <jmkasunich> not sure yet
[04:25:34] <mshaver> I had a heck of a time just finding these license files...
[04:25:44] <jmkasunich> we need to look at the software license closely
[04:26:00] <jmkasunich> its a heck of a lot shorter than the megacore license
[04:26:04] <petev> I dont' see why altera would care about the constraint file
[04:26:22] <petev> it's totally design dependent and contains no IP of theirs
[04:26:28] <mshaver> Did he use the web version of Quartus?
[04:26:40] <jmkasunich> you'll have to ask him
[04:26:52] <jmkasunich> I'm sure he didn't buy any software from them
[04:27:00] <mshaver> That license file link is in my e-mail
[04:28:15] <mshaver> petev: Common sense is nearly unrelated to the interpretation of legal stuff
[04:28:49] <petev> true, but they wouldn't want to waste money on legal fees over nothing
[04:29:04] <jmkasunich> I don't have a copy of the altera stuff, and I'm not about do register for it just to examine the license that comes with it (which may or may not be the license that you found)
[04:29:09] <petev> all it would do is hurt sales of their IC on the pluto board
[04:29:17] <jmkasunich> petev: that is not the point
[04:29:28] <jmkasunich> Paul is FUDding about the threat, not the reality
[04:29:44] <mshaver> <what john said>
[04:29:52] <jmkasunich> we have to show that we are permitted to release the firmware, not just that they won't bother sueing us
[04:30:10] <petev> I understand, but I have used megacores before
[04:30:16] <mshaver> We must present an affirmative defense
[04:30:23] <jmkasunich> I bet you had to license them....
[04:30:23] <petev> the idea there is you are licensing some IP from altera or a partner
[04:30:30] <jmkasunich> exactly
[04:30:33] <petev> they don't want you to then take that and make an ASIC
[04:30:37] <petev> then they get no money
[04:30:45] <petev> that's what all the legal BS is about
[04:30:55] <jmkasunich> before you arrived, I already talked to matt about the megacore issue - that license is totally irrelevant to Jeffs work
[04:31:04] <jmkasunich> the design software license is not
[04:31:10] <jmkasunich> but it is also a lot less restrictive
[04:31:27] <jmkasunich> matts message to the list focused the attention on the wrong license unfortunately
[04:31:33] <petev> I didn't see anything in the design sw license, but I'm no lawyer
[04:32:10] <mshaver> Right, we understand, but contracts are interpreted according to the "four corners doctrine", it's not the intent, it's what's written within the four corners of the page
[04:32:35] <jmkasunich> as long as you are on the right page
[04:32:55] <jmkasunich> the design software license makes no claim whatsoever to the output of a design
[04:33:04] <mshaver> I'll admit I might have been mistaken on that point
[04:33:09] <jmkasunich> if it did, Altera's corporate customers would drop them like hot potatoes
[04:33:36] <jmkasunich> my employers are not going to give Altera even the tiniest slice of the rights to my work
[04:33:37] <petev> I'm already dropping them after hearing thier tool drops copyright shit in your files
[04:33:44] <petev> that is rediculous
[04:34:07] <mshaver> Altera's corporate customers are not affected by this at all, they pay for a license to program chips, then distribute only the chips
[04:34:52] <mshaver> or at worst, a .bin that is simply clocked into the chip
[04:35:21] <jmkasunich> nope
[04:35:26] <jmkasunich> thats not how fpgas work
[04:35:40] <jmkasunich> they pay for a license to use the tools to develop designs (or they use the no-cost tools)
[04:35:50] <jmkasunich> they pay for the chips themselves (blank silicon)
[04:36:03] <jmkasunich> and then they distribute the bit files to program them
[04:36:11] <jmkasunich> the main only restriction
[04:36:28] <jmkasunich> the main restriction is that you can't use those bitfiles to program somebody elses chips
[04:36:34] <petev> you usually only need to buy the tool if you are using one of the latest and greatest parts that aren't supported in the free version
[04:36:43] <jmkasunich> right
[04:36:47] <petev> which doens't really work anyhow
[04:36:55] <jmkasunich> and in any case, you still own the output files
[04:36:55] <petev> the bit files are totally IC specific
[04:37:17] <mshaver> but they don't redistribute any of the source used to compile that bitfile - that's what we're doing that's different
[04:37:41] <petev> but that source is jelpers IP, not altera
[04:37:53] <petev> I have libraries of HLD that get used in many parts
[04:38:04] <jmkasunich> we own the source even MORE than we own the output bitfile
[04:38:11] <petev> if I use it in an Altera, no way does that mean I can't use it elsewhere
[04:38:37] <jmkasunich> anybody (corporate or free software) is free to take the Verilog and compile it using other tools, for other chips
[04:38:47] <petev> right
[04:38:50] <jmkasunich> they NEVER own ANY of the source
[04:39:22] <jmkasunich> they MAY "own" some of the output, because it contains stuff that their toolchain put in it, but they only put a few limited restrictions on what you can do with the output
[04:39:43] <jmkasunich> because to restrict it excessively would be commercial suicide
[04:40:27] <petev> I think Paul didn't have a clue, or just wanted to make trouble when he saw the erroneous copyright
[04:40:35] <mshaver> We need to locate the text that governs the redistribution of the "toolchain output" like the constraints file, etc.
[04:41:15] <petev> constraints are an input
[04:41:21] <mshaver> Yes <trouble>, but once an issue is raised it must be addressed
[04:41:29] <petev> they set the timing and other parameters that the tool needs to meet
[04:42:30] <mshaver> yes, but the names like "ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON" are Altera IP. No?
[04:42:53] <petev> no, I think they are Altera keywords
[04:43:00] <petev> it's like a keyword in C++
[04:43:08] <petev> or VHDL or whatever
[04:43:10] <jmkasunich> mshaver: I can't speak for altera
[04:43:12] <jmkasunich> oops
[04:43:26] <jmkasunich> for altera's toolchain, but xilinx has similar constraint files
[04:43:34] <jmkasunich> they have their own editor to create them
[04:43:57] <jmkasunich> but the keywords are completely described in the documentation, and it is quite possible to create the constraint file manually
[04:44:29] <mshaver> but C++ is a standard that, for some reason I haven't researched, is publically usable to define a language
[04:44:44] <jmkasunich> what does that have to do with anything?
[04:45:03] <jmkasunich> it doesn't matter whether the language is standard or proprietary
[04:45:29] <jmkasunich> if you tell me how to write a program in your proprietary language, that doesn't mean you own the program that I write
[04:45:33] <petev> my point was that I don't see how using the language could make the IP belong to Altera
[04:45:40] <jmkasunich> exactly
[04:45:45] <petev> if it did, nobody would use their parts
[04:46:11] <jmkasunich> there is a certain syntax for writing a constraint file, just like there is a certain syntax for invoking a program from the command line
[04:46:21] <jmkasunich> using the syntax doesn't mean giving up copyright
[04:48:41] <mshaver> No, but the parameters of their constraint files are specific to Altera's development software. We are revealing to non-licensees the names and potential values of these parameters when we redistribute the file.
[04:50:15] <jmkasunich> as I said, I haven't looked yet, but I bet you those names and values are in the manual
[04:51:42] <mshaver> For example, it might be that the fact that Altera has a parameter like "ALLOW_POWER_UP_DONT_CARE OFF" which is specific to their tools and which, because it is adjustable, or definable gives their system a competitve advantage and is copyrighted.
[04:52:12] <LawrenceG> tfmacz: hi Ted
[04:52:20] <mshaver> I know I'm reaching here, but I'm taking the other side in this debate
[04:52:36] <tfmacz> LawrenceG, Hi
[04:52:49] <petev> there are only reasons for Altera to want this IP distributed and non for them not to
[04:53:00] <petev> I don't think we should waste a lot of time on it
[04:53:27] <jmkasunich> it took me a couple days to figure out how to do the xilinx stuff without using their stupid IDE/GUI
[04:53:34] <jmkasunich> the real tools are all command line programs
[04:53:55] <jmkasunich> the docs for the command line programs almost certainly tell you what those options are
[04:54:13] <jmkasunich> they do NOT force you to use their GUI, or their constraint editor
[04:54:35] <petev> right
[04:54:59] <cradek> then can we just rewrite the file? (maybe that's what jepler did)
[04:55:23] <jmkasunich> I think all he did was remove their header
[04:55:27] <mshaver> __I__ sure don't want to waste any more of my time! Monday, I'll call Altera & explain this, give them the cvs URL & let them render their opinion.
[04:55:32] <tfmacz> cradek, Hi Chris
[04:55:39] <petev> jepler wrote the file to begin with, he had to pick the approriate settings, maybe he used their editor
[04:55:43] <cradek> hi
[04:55:47] <jmkasunich> mshaver: please do not do that
[04:55:55] <mshaver> why?
[04:56:14] <tfmacz> cradek, I like the image2gcode that you added to Axis
[04:56:21] <jmkasunich> if somebody is going to talk to atlera about Jeff Epler's design, it should be Jeff Epler - since only he can describe exactly what he did and did not use from their toolchain
[04:56:51] <mshaver> Oh, OK! If he wants to do it that's even better!
[04:57:02] <jmkasunich> I don't know if he wants to or not
[04:57:08] <jmkasunich> he's not around at the moment
[04:57:24] <mshaver> well, it's not like it's an emergency...
[04:58:40] <jmkasunich> http://www.altera.com/literature/hb/qts/qts_qii52001.pdf is the manual for their constraints editor (they call it an assignment editor)
[04:59:05] <mshaver> It just irks me to no end when these issues are brought up over & over, and I'd love to see all the nails driven home that settle this once and for all!
[04:59:11] <jmkasunich> I'm downloading the manual for the step in the toolchain that reads that file
[05:01:20] <jmkasunich> or not... got another gui tool manual
[05:02:25] <mshaver> What is Paul's motivation here? Does anyone know?
[05:03:04] <cradek> he's been this way ever since he resigned his board position in a "huff"
[05:03:24] <jmkasunich> mshaver: have you seen his writings on his tuxcnc website?
[05:03:25] <cradek> he wants people to be scared of emc2 so he has time to write his own derivative of emc
[05:03:39] <cradek> (which is FUD by definition)
[05:03:56] <mshaver> jmkasunich: yes, found it the other day, sort of funny actually!
[05:04:14] <cradek> yeah I like the part about voodoo dolls or whatever it was
[05:06:13] <cradek> btw he'll read this archive tomorrow (hi paul!)
[05:06:15] <mshaver> cradek: Between things like this, and sniping from the Mach camp about how much we suck, even to people who never gave the EMC more than 5 minutes to evaluate, I was very happy when you took over this mess ;)
[05:06:38] <cradek> ha
[05:06:39] <jmkasunich> hah, found it
[05:06:43] <jmkasunich> http://www.altera.com/literature/manual/mnl_qsf_reference.pdf
[05:06:53] <jmkasunich> its 4 meg, don't download it unless you care...
[05:06:59] <jmkasunich> that lists all those silly options
[05:07:01] <cradek> you over-estimate my role - I'm only part of a team
[05:07:24] <jmkasunich> I think that was a collective "you"
[05:07:27] <mshaver> yes, the part that gets blamed!
[05:08:07] <tfmacz> LawrenceG: how about this
[05:08:09] <cradek> yes, paul has a particular dislike of me, which is funny because he's the one who welcomed me into the project
[05:08:24] <jmkasunich> "ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION" is defined on page 2-129
[05:08:24] <mshaver> well, I guess if they list the params in a publically avaiable doc, we can't be doing very much wrong here
[05:08:38] <jmkasunich> none of those directives can be considered proprietary information
[05:08:44] <mshaver> agreed
[05:08:50] <jmkasunich> their editor is just a convenience tool, the output file can be created manually
[05:09:40] <jmkasunich> even when you use the tool, the output is directly related to your input into the GUI, which means under copyright law you own the output
[05:11:12] <mshaver> ok, just looking at the other files in pluto_firmware to see if there's anything else, probably not....
[05:13:24] <mshaver> wow, I catted pluto....rbf to my terminal & now my term is pretty funky ;)
[05:13:44] <jmkasunich> I think that is the binary bitstream ;-)
[05:14:47] <mshaver> yep
[05:15:08] <mshaver> the .v files, they're dome sort of logic description language?
[05:15:21] <jmkasunich> verilog I think
[05:15:37] <mshaver> ok, so that's not a problem
[05:15:46] <jmkasunich> those are the "source code"
[05:15:59] <jmkasunich> jeff owns thost 110%
[05:16:03] <jmkasunich> those
[05:17:01] <mshaver> the .pin file looks pretty harmless, it just describes how the device was routed
[05:18:14] <mshaver> Unless the .bin file contained some of those proprietary cores or other licensable IP, the .bin should be redistributable, so I guess it's all OK.
[05:18:35] <mshaver> I'm out of arguments.
[05:18:40] <mshaver> EOF
[05:19:25] <cradek> mshaver, are you still geographically near fred p./nist?
[05:20:13] <cradek> I have some that nist lathe on loan, and I'd like to get it back to fred p.
[05:20:27] <cradek> err, pretend that was english
[05:20:31] <mshaver> In 1983 I got laid off from amy first computer job at Burroughs. A guy I worked with asked me what I was going to do. I said I was going to clean up my environment, and go to end of job...
[05:21:14] <mshaver> cradek: yep, down the road a piece
[05:21:35] <cradek> it would be great if I could send it back his way through you - can you spare the space on the return trip after fest?
[05:21:50] <mshaver> sure, no problem
[05:21:52] <cradek> I could ship it but it's so large that seems risky
[05:21:54] <cradek> thanks, that's great
[05:22:22] <mshaver> I'm sure you can keep it as long as you need it, if you've got more you want to do
[05:22:41] <cradek> I got a message from someone at nist today - she wants to arrange paperwork so I can keep it longer
[05:22:41] <mshaver> If it goes back, it might get thrown away
[05:22:52] <cradek> oh, eek
[05:23:07] <mshaver> yep, that happens all the time
[05:23:29] <cradek> since I have retrofitted my own lathe the only thing that could still be useful on the nist lathe would be the spindle control
[05:23:32] <cradek> (I don't have that)
[05:24:18] <cradek> someday I want to do CSS, but rigid tap will be first
[05:24:21] <mshaver> You know, I'm going to do some lathe stuff for Smithy, so i can return it if you're done & check it out myself
[05:24:32] <mshaver> I'm supposed to do CSS
[05:24:39] <mshaver> for them
[05:24:41] <cradek> oh :-)
[05:24:55] <mshaver> unless you do it first/soon :)
[05:25:12] <cradek> it's partly done (we moved spindle control into realtime)
[05:26:03] <mshaver> good - I need to buckle down, stop reading the e-mail list & do some actual work.
[05:26:30] <cradek> have you played with lathe tool shape comp? it's pretty neat
[05:27:03] <cradek> we could do gouge protection too - the angles are already in the tool table
[05:27:26] <cradek> too many projects :-)
[05:28:13] <mshaver> no, I even have a Hardinge HNC retrofitted in my basement & haven't done any software yet
[05:28:39] <mshaver> I get waylaid all the time with life stuff
[05:29:30] <cradek> we should be careful not to duplicate work...
[05:29:43] <cradek> lately we seem to want to tackle the same things
[05:30:26] <tfmacz> cradek: Need something else to work on???
[05:31:21] <cradek> tfmacz: ask not what your Free software can do for you
[05:31:52] <tfmacz> cradek: need to add a spindle speed dialog to the image-to-gcode setup
[05:32:22] <tfmacz> cradek: don't cut much at 1000rpm
[05:32:35] <cradek> hmm
[05:32:44] <cradek> that doesn't sound too hard
[05:33:12] <cradek> you give me too much credit for i2g - it's mostly jepler's work based loosely on my older work
[05:33:38] <tfmacz> I have been using the image-to-gcode script from the command line pipes to a file, then I can edit the spinde speed
[05:33:46] <mshaver> cradek: true (writing something about this debate here on the list)
[05:33:51] <cradek> right, good workaround
[05:34:26] <tfmacz> cradek: so I should ask Jeff about it???
[05:34:34] <cradek> spindle override might also be a workaround
[05:34:43] <cradek> yes, or submit a feature request in the tracker on sourceforge
[05:35:33] <cradek> or submit a patch! :-)
[05:35:57] <tfmacz> cradek: would need to be able to take the override to 1000% to be useful
[05:37:06] <tfmacz> I will have to keep bugging LawrenceG about that...waaaaay beyond me...
[05:37:06] <cradek> possible, but silly
[05:37:19] <cradek> about what?
[05:37:32] <tfmacz> cradek: a patch..
[05:38:01] <tfmacz> cradek: he suggested doing that
[05:40:57] <LawrenceG> tfmacz: I heard that....
[05:54:21] <cradek> tfmacz: done
[05:57:27] <tfmacz> cradek: cool
[06:00:24] <petev> jmk, you still there?
[06:00:29] <jmkasunich> yeah
[06:00:43] <petev> I was cleaning out some old stuff and found some old dev tools
[06:01:00] <petev> I have an old promice and some 80186 sw tools
[06:01:05] <petev> you interested in any of it?
[06:01:10] <petev> I have no use for it
[06:01:14] <jmkasunich> neither do I
[06:01:28] <jmkasunich> I only develop for the PC
[06:01:38] <petev> the promice could be used for other projects, but I just don't use through hole stuff anymore
[06:01:39] <cradek> I would have a couple years ago (if it would emulate 2716 prom)
[06:01:46] <petev> anyone else interested?
[06:02:08] <petev> I can check on that cradek
[06:02:25] <cradek> thanks anyway, project long over
[06:03:09] <petev> if anyone knows any DIY type that would want this stuff, let me know
[06:03:27] <petev> I also have some old Borland x86 compilers and the Pharlap stuff for embedded
[06:03:56] <cradek> heh, me too (somewhere)
[06:04:08] <cradek> majorbbs used pharlap
[06:04:29] <jmkasunich> I have Watcom C/C++ around here somewhere ;-)
[06:04:42] <petev> yeah, I have that one too ;-)
[06:04:45] <cradek> one of those is free (of cost) now, I forget which one
[06:05:01] <petev> used to be good tools at the time
[06:08:42] <mshaver> OK, new e-mail on the list explaining the Pluto stuff. Should put it to rest. Something simillar should probably be written up for the other firmware directories.
[06:08:59] <cradek> thanks for doing that matt
[06:10:48] <mshaver> no problem - going to bed now - or to eat a sandwich, probably both...
[06:11:02] <cradek> me too, goodnight
[06:11:12] <petev> gn
[06:11:57] <jmkasunich> 2am again
[06:11:56] <jmkasunich> dammit
[13:43:16] <jepler> for anyone who still cares about the quartus settings file: while I think it's asinine that quartus puts a copyright on a file holding information that I entered, I did the following asinine dance:
[13:44:51] <jepler> made a Python program that had a list of the settings and their values, made by typing in the settings I read from the other file (which are purely functional, since there's no other way to request that signal X go on pin Y, for example)
[13:45:00] <jepler> then i ran that program
[13:45:18] <jepler> then I forgot all about it -- this was the *last* time this came up, a few months ago.
[13:45:51] <jepler> fast forward to yesterday -- the machine where I had done had been reinstalled in the mean time, and I was only able to find the output file, not the python program
[13:46:08] <jepler> I decided to check in the output file anyway
[14:29:28] <jepler> hi ray
[14:31:54] <steves_logging> steves_logging is now known as steve_stallings
[14:52:09] <rayh> hi jeff.
[15:12:58] <rayh> logger_dev: bookmark
[15:12:58] <rayh> Just this once .. here's the log:
http://www.linuxcnc.org/irc/irc.freenode.net:6667/emcdevel/2007-03-17.txt
[15:26:09] <rayh> I see someone was talking about 1000% override last night late. Anyone know what that was about.
[15:31:18] <jepler> rayh: I think that was because image-to-gcode had hard coded 1000RPM, and he wanted more
[15:31:31] <jepler> rayh: chris fixed it by letting the RPM be specified directly
[16:28:39] <rayh> ah okay.
[16:35:15] <rayh> a "work around." I tested large overrides with feedrate and they seem to work fine in the tcl stuff.
[20:28:05] <alex_joni> hello all
[20:28:57] <cradek> hi alex
[20:29:10] <jepler> good afternoon
[20:29:21] <alex_joni> jepler: that's debateable
[20:29:27] <alex_joni> both aspects really
[20:29:27] <jepler> alex_joni: it's clearly afternoon where I am
[20:29:36] <jepler> sorry to hear that
[20:30:12] <alex_joni> time will make it right
[20:31:36] <jepler> cradek: I think I need to back-port all these image-to-gcode changes -- I forgot that the tool shape stuff was all wrong, which I discovered when I did gdepth...
[20:32:00] <cradek> jepler: great, do it soon then...
[20:32:16] <jepler> cradek: do you think doing hal_input would be OK too?
[20:32:37] <cradek> it's totally isolated?
[20:32:40] <alex_joni> cradek: yes
[20:32:43] <jepler> yes, it's two additional files
[20:32:45] <alex_joni> and requested
[20:32:53] <cradek> no harm in that
[20:33:18] <jepler> I'll get to it -- I hope one of you will check that I got the packaging right
[20:34:38] <LawrenceG> jepler: cradek: hi guys.... I am thinking of adding a sync pin to the pwmgen block so I can sync the pwmgen output to the 60hz line zero crossings... any comments?
[20:34:58] <alex_joni> jepler: I struggle to keep up
[20:35:34] <alex_joni> right now I'm wondering why I <strike>spent</strike>wasted so much time on the mailing list reading FUD
[20:35:52] <jepler> alex_joni: I skipped over it -- "more heat than light" as they say
[20:36:13] <alex_joni> 98% for a lightbulb?
[20:37:11] <jepler> LawrenceG: hm -- I'm not quite sure how that would fit into the pwmgen algorithm
[20:37:43] <cradek> LawrenceG: don't you want a triggerable oneshot with configurable on-time?
[20:37:43] <jepler> LawrenceG: maybe there's some way to combine pwmgen with 'edge' or 'flipflop'?
[20:38:06] <jepler> yes there's also 'oneshot'
[20:38:26] <jepler> unfortunately, oneshot.N.width / edge.N.out-width-ns are both parameters rather than pins
[20:38:27] <alex_joni> what's 60Hz ?
[20:38:31] <jepler> alex_joni: US power
[20:38:37] <alex_joni> * alex_joni grins :P
[20:38:39] <LawrenceG> jepler: it may be better to make a new block as one doesnt need the complexity of 8 pwm pins
[20:40:10] <LawrenceG> I am playing with making a cheap spindle control using ssr and pwmgen... with it being none synced, there is some speed hunting as the pwmgen freq beats with the line freq
[20:41:01] <LawrenceG> pwm duration gets radom additions to leading and trailing edges due to triac action
[20:41:19] <LawrenceG> but it sort of works for 3 or 4 speeds
[20:43:12] <jepler> LawrenceG: I think I'd try my hand at a new, less generic component.
[20:43:25] <LawrenceG> sync pin -> 0-8ms delay( to sync with real zero crossing) -> 0-8ms phase control
[20:43:32] <jepler> LawrenceG: have you read the source for any of the ".comp" components? they can be quite simple
[20:44:27] <LawrenceG> yeah... I am just exploring the possiblities now... all the parts are there, smop
[20:45:50] <LawrenceG> I am thinking open loop for now, but it could be generalized to accept speed feedback as well
[20:46:45] <LawrenceG> it would be nice to use existing encoder and pid blocks for the feedback
[20:46:47] <jepler> would it be possible to re-use the existing pid module for that?
[20:47:13] <LawrenceG> great minds think alike
[20:47:15] <jepler> yep
[20:49:34] <LawrenceG> I dont think anyone has done a speed control in hal... the lathe code comes close with the spindle feedback, but it is just syncing other moves and not correcting spindle speed
[20:49:42] <jepler> so this component of yours will take a reference signal, a width, and a phase, and output pulses of the requested width that are in the given phase with the reference?
[20:51:54] <LawrenceG> sync pin in(120hz likely), commanded speed input from motion(ie S1000), and an ouput pin that pulses 0..8.3ms on
[20:52:44] <LawrenceG> there will need to be a fudge factor input pin to get the sync signal actually lines up with the ac zero crossing the triac sees
[20:53:31] <LawrenceG> feedback is another optional input
[20:54:07] <LawrenceG> basically a $1000 light dimmer
[20:54:10] <jepler> hah
[20:55:13] <alex_joni> does Hal Config work for you?
[20:55:17] <LawrenceG> quite a bit easier then generating step pulses!
[20:56:19] <jepler> alex_joni: anything in particular about it?
[20:56:24] <alex_joni> jepler: running it?
[20:56:39] <alex_joni> I selected sim->tkemc, and the Hal Config from the menu
[20:56:46] <alex_joni> and it barfs (something about a signal)
[20:57:54] <jepler> Error in startup script: node "sig+XYZvel" already exists
[20:57:57] <jepler> yeah me too
[20:58:06] <alex_joni> yup, that
[20:58:33] <jepler> in 2.1 from the package, I only get "Hal Show", not "Hal Config"
[20:58:35] <jepler> "Hal Show" works
[20:58:41] <alex_joni> Hal Config is not in 2.1
[20:58:57] <alex_joni> yeah, I know hal show is supposed to work
[20:59:20] <alex_joni> Hal Config is ray's attempt at making an HAL editing thingie
[20:59:33] <alex_joni> but he had problems on writing the output I think
[21:00:04] <jepler> this bug looks familiar, like it's something I had fixed in hal show once..
[21:00:24] <jepler> RCS file: /cvs/emc2/tcl/bin/halshow.tcl,v
[21:00:30] <jepler> revision 1.4
[21:00:31] <jepler> date: 2006/07/23 20:10:06; author: jepler; state: Exp; lines: +4 -4
[21:00:31] <jepler> fix for error: Error in startup script: node "sig+XYZvel" already exists
[21:00:31] <jepler> ----------------------------
[21:00:40] <jepler> maybe this can be applied to hal config as well
[21:00:54] <alex_joni> I'll check
[21:00:59] <alex_joni> thanks for the pointer
[21:04:09] <alex_joni> yup, that fixes it
[23:52:42] <jmkasunich> LawrenceG: still here?
[23:53:26] <jmkasunich> I saw your thoughts about doing SCR control when I read back yesterday
[23:53:38] <jmkasunich> that is definitely a candidate for a new HAL component
[23:53:56] <jmkasunich> and I will do it sooner or later if you don't
[23:54:50] <alex_joni> hi jmkasunich
[23:54:57] <jmkasunich> hi alex
[23:57:38] <jmkasunich> LawrenceG: a good generic phase control module would have a sync input (for the zero cross signal), 1, 2, 3, or 6 outputs (for single phase and three phase, triac and scr bridges), an offset parameter used to tweak the timing, and a single control pin for an input
[23:58:10] <jmkasunich> the control pin would control the lag between the zero cross input and the output(s)
[23:58:28] <jmkasunich> any additional control and/or feedback would be done with other blocks, like PID, etc