#emc-devel | Logs for 2006-12-11

[00:05:58] <jmkasunich> grrr... the xilinx page for download (and installation instructions) is down for maintainence
[00:06:14] <jmkasunich> I already downloaded the file, its a massive script
[00:06:51] <jmkasunich> I guess I could just run it an see what happens
[01:03:47] <SWPadnos> it's only like 1.2G ;)
[01:06:38] <jmkasunich> well, it seems to have worked
[01:06:47] <jmkasunich> worked better the second time when I ran it as root
[01:06:55] <SWPadnos> heh
[01:07:15] <SWPadnos> I think it may even take advantage of multiple cores, at least for the place and route phase
[01:08:10] <jmkasunich> wow, what an install
[01:08:16] <jmkasunich> 2476 subdirectories
[01:08:21] <SWPadnos> the design of the mesa FPGA is basically a bus architecture
[01:08:23] <SWPadnos> heh
[01:08:34] <SWPadnos> not multimaster and all that jazz like wishbone
[01:09:00] <SWPadnos> but you can mix and match peripherals reasonably easily
[01:09:25] <jmkasunich> I take it you know at least a little of whatever language that is written in?
[01:09:35] <SWPadnos> if you want to see how the code is structured, look at hostmot5-4e.vhd - that's the "master file" which instantiates all the peripherals
[01:09:40] <SWPadnos> a little - it's not too hard to understand
[01:09:54] <SWPadnos> knowing enough to "invent" something is a little trickier
[01:11:24] <SWPadnos> I can also send you the hostmot5-8e.vhd file I have, so you can see the differences between a 4-axis and an 8-axis units
[01:11:25] <SWPadnos> uinit
[01:11:27] <SWPadnos> unit
[01:11:29] <jmkasunich> hmm, I have a lot of learing to do
[01:11:34] <SWPadnos> heh
[01:11:35] <jmkasunich> learning
[01:11:48] <SWPadnos> something to read on the plane ...
[01:11:55] <SWPadnos> or in the car or whatever
[01:12:05] <jmkasunich> plane ride is only an hour
[01:12:15] <SWPadnos> no time for a laptop - better bring a printout ;)
[01:12:35] <jmkasunich> first thing in the morning I can't read anything the requires brainpower
[01:12:40] <SWPadnos> heh
[01:12:47] <SWPadnos> oh - morning flight. didn't know that
[01:13:21] <jmkasunich> I really wish they used schematics instead of vhdl
[01:13:33] <SWPadnos> you can do that, but you have to pay for the privilege
[01:13:44] <SWPadnos> around $12000, in some cases ;)
[01:13:50] <jmkasunich> a (well done) schematic makes heirarchy and structure much more visible than a bunch of text
[01:14:19] <SWPadnos> then again, "a <= a + 1" makes more sense than a schematic ...
[01:14:44] <jmkasunich> if the level of the schematic is too low, I agree 110%
[01:14:55] <jmkasunich> block diagram would be a better term
[01:15:04] <jmkasunich> msi/lsi view of things
[01:15:05] <SWPadnos> sure
[01:15:44] <SWPadnos> I've imported the mesa code into Altium, which has a function to convert a VHDL file into a schematic symbol
[01:16:01] <SWPadnos> so I can place a group of encoders on a schematic, and wire them to the I/O pins ...
[01:16:14] <jmkasunich> actually, making up a block diagram for the existing config might be a good exercise in understanding the language
[01:16:28] <SWPadnos> yeah, probably
[01:16:45] <SWPadnos> the mesa card is a bit more complex than it has to be, because they've made it very flexible
[01:16:48] <jmkasunich> looks like kate understands vhdl, there is syntax highlighting
[01:16:59] <SWPadnos> yep
[01:18:23] <SWPadnos> actually, look for "makecounters" in hostmot5-4e.vhd
[01:18:51] <jmkasunich> found it
[01:19:22] <SWPadnos> I can give you a bigfix if you like ;)
[01:19:25] <SWPadnos> bugfix
[01:19:42] <jmkasunich> whats the bug?
[01:19:58] <SWPadnos> apparently, the encoder inputs aren't in the right place
[01:20:13] <jmkasunich> wrong pins on the part you mean?
[01:20:23] <jmkasunich> or wrong address on the bus? or?
[01:20:37] <SWPadnos> if you look at the quada, quadb, and index assignments, you can see that they get assigned to sequential locations
[01:20:48] <jmkasunich> yep
[01:20:54] <SWPadnos> I'm not sure - it looks like the counter port map is wrong
[01:21:09] <SWPadnos> those addresses should be i*4 + {0,1,2,3}
[01:21:14] <jmkasunich> you see, first I have to understand what a port map is
[01:21:14] <SWPadnos> (3 for indexmask)
[01:21:18] <SWPadnos> heh
[01:22:14] <SWPadnos> hmmm - actually, don't change anything yet, the code in CVS doesn't match either version I have here
[01:22:30] <jmkasunich> I'm not about to change anything
[01:22:45] <SWPadnos> heh - that was my view as well
[01:23:06] <SWPadnos> until I could verify that I can generate the same bitfile that's there, with the code that's there, I didn't want to mess with anything
[01:23:24] <jmkasunich> have you installed the toolset yet?
[01:23:26] <SWPadnos> of course, you don't necessarily get the same bitfile, even if the functionality of the FPGA is the same
[01:23:37] <SWPadnos> I have, but it expired. I have a licensed version
[01:23:57] <SWPadnos> I need to reinstall, but I haven't decided exactly how/where to install the license yet
[01:23:59] <jmkasunich> is place-and-route deterministic? ISTR using a seed value back in the day
[01:24:15] <SWPadnos> no, I think it can vary
[01:24:21] <jmkasunich> yuck
[01:24:34] <SWPadnos> yeah - it's like a PCB. same connections, but differnt path to get there
[01:24:42] <SWPadnos> the wiring is in the bitfile as well
[01:24:49] <jmkasunich> I know
[01:25:02] <jmkasunich> but computers are deterministic
[01:25:13] <SWPadnos> in theory
[01:25:30] <jmkasunich> if you invoke an autorouter, on a specific input, you should get a specific output, unless they actually force non-determinism
[01:26:26] <SWPadnos> optimization may not be, depending on the methods used (like statistical methods))
[01:26:31] <jmkasunich> way back when I was doing FPGAs the last time, the place and route accepted a seed value for the internal random number generator, to get repeatable results
[01:26:34] <SWPadnos> monte-carlo adds randomness
[01:26:50] <SWPadnos> that may still be the case, but we don't have Mesa's seen number ...
[01:26:51] <jmkasunich> (they used the random generator for the "simulated annealing" autoplace algorithm
[01:26:55] <SWPadnos> seed
[01:27:09] <jmkasunich> true
[01:27:37] <SWPadnos> have you seen the write-ups about genetic algorithms for FPGAs?
[01:28:06] <jmkasunich> it would be nice to be able to detect the development tools in ./configure, and let make m5i20 build the bitfiles
[01:28:17] <jmkasunich> using a seed that is in the CVS, so everybody gets the same thing
[01:28:19] <SWPadnos> that would be interesting, no doubt
[01:28:43] <jmkasunich> the bitfiles would also be in CVS, so people without the tools don't get stuck
[01:28:45] <SWPadnos> but it would also add minutes to the build (unless the Xilinx tools are shitloads faster when not invoked by LabView)
[01:29:20] <jmkasunich> it would only do that for people who A) have the tools, and B) modified the vhdl source
[01:29:23] <SWPadnos> yes
[01:30:17] <jmkasunich> so, back to hostmot5
[01:30:21] <SWPadnos> ok
[01:30:23] <jmkasunich> component counter
[01:30:27] <jmkasunich> port{
[01:30:43] <jmkasunich> list of all the stuff that leaves/enters that component
[01:30:45] <jmkasunich> }
[01:30:48] <jmkasunich> end component
[01:30:53] <jmkasunich> where's the beef?
[01:31:10] <SWPadnos> architecture dataflow of hostmot5_4 is ...
[01:31:15] <SWPadnos> (next line)
[01:31:52] <SWPadnos> add buttloads of signals, intantiate all the peripherals, and connect them
[01:32:17] <jmkasunich> line 85 you mean?
[01:32:23] <SWPadnos> dunno - looking at cvs
[01:32:35] <SWPadnos> just after the "end component" you mentioned
[01:32:52] <jmkasunich> ok, these files are very different
[01:33:04] <jmkasunich> starting from the top, I have
[01:33:34] <jmkasunich> comments, library IEEE, use IEEE.blah, entity HoseMot5_4 is blahblahblah
[01:33:45] <jmkasunich> end HostMot5_4
[01:33:58] <jmkasunich> architecture dataflow of Hostmot5_4 is
[01:34:01] <jmkasunich> blah blah blah
[01:34:43] <jmkasunich> entire rest of the file blah blah
[01:34:46] <jmkasunich> end dataflow
[01:34:55] <SWPadnos> that blah blah blah is a lot of signals, then instantiation of the things in the other .vhd files
[01:35:01] <jmkasunich> the counters block is somewhere in the middle of the dataflow block
[01:35:17] <jmkasunich> I kinda follow that
[01:35:27] <SWPadnos> I don't know how it figures out where to find the definitions for the functional blocks (like "include" would do for C)
[01:35:50] <jmkasunich> I got confused cause you said the dataflow thing started after the counter block, but here the counter block is inside the dataflow
[01:36:02] <SWPadnos> ah - sorry
[01:36:15] <SWPadnos> the beef of the coutner is in countere.vhd
[01:36:33] <jmkasunich> ok, I'm not gonne dive into that
[01:36:51] <SWPadnos> it's a bit complex - there are a lot of modes and clears and index options ...
[01:37:17] <SWPadnos> I haven't really tried to get through it yet - want to learn some VHDL for real first ;)
[01:37:23] <jmkasunich> if I was gonna do one to be "our" encoder counter, I'd make it exactly match the canoncial interface
[01:37:49] <jmkasunich> you got me curious about the lack of an "include"
[01:37:53] <SWPadnos> heh
[01:38:02] <jmkasunich> grep says countere doesn't appear anywhere in any of the files
[01:38:26] <SWPadnos> I had emailed PeteW about that "where's the 'project file'?", he said there isn't one, just load up hostmot and it'll work
[01:38:38] <jmkasunich> why don
[01:38:44] <SWPadnos> damfino - countere has a definition for counter though ...
[01:38:44] <jmkasunich> why don't I try that ;-)
[01:38:56] <SWPadnos> that worked for Altium, which is surprising
[01:40:18] <jmkasunich> opening the vhd file just seems to have opened it in an editor
[01:40:51] <jmkasunich> I think I'm gonna have to define a new project and tell it what files are part of the project
[01:40:54] <SWPadnos> hmmm - maybe he said "make a project and stick all the files into it" ;)
[01:40:58] <jmkasunich> either that or RTFM
[01:40:58] <SWPadnos> right
[01:41:27] <SWPadnos> I had some trouble with the pin file because I'm using a different system
[01:43:42] <jmkasunich> * jmkasunich reads "quick start tutorial"
[01:43:58] <SWPadnos> oh - that sounds helpful
[01:46:28] <SWPadnos> I guess I should just make the decision to use VMWare for my Windows software, and be done with it. the only problem is, I'm not sure Altium can communicate with the devkit (or other microcontroller programmers, for that matter) from within a VM
[01:48:25] <jmkasunich> dumbass dialog box
[01:48:38] <jmkasunich> you browse your way to a source file and add it to the new project
[01:48:55] <SWPadnos> and it resets to your home dir or some other stupid action
[01:49:03] <jmkasunich> then go to do another one, does it remember the dir from the last one? Nooooooo..... it goes back to the project dir
[01:49:25] <SWPadnos> can you multi-select?
[01:50:10] <jmkasunich> yes ;-)
[01:50:12] <jmkasunich> thanks
[01:50:33] <SWPadnos> no problem :)
[01:51:15] <jmkasunich> well, I have a project now
[01:51:50] <SWPadnos> as long as hostmot5-4e is the "master", it should work (I think)
[01:52:23] <jmkasunich> doing a syntax check
[01:52:53] <SWPadnos> I'd be curious to know how long it takes to generate the bitfile
[01:53:08] <jmkasunich> I have a way to go to get there
[01:53:21] <jmkasunich> for instance it still knows nothing about the desired pinout
[01:53:28] <SWPadnos> that's what the pin file is for
[01:53:43] <jmkasunich> right, but I haven't imported that into the project yet
[01:53:57] <SWPadnos> I don't think that specifies the actual part - you'll need to do that too
[01:54:07] <SWPadnos> one sec - I'll look at it
[01:54:12] <jmkasunich> that was part of the "new project" process
[01:54:30] <SWPadnos> oh
[01:54:51] <SWPadnos> it's an XC2S200 in the PQ208 package
[01:55:44] <jmkasunich> I guessed right ;-)
[01:55:51] <SWPadnos> heh :)
[01:58:35] <SWPadnos> amazingly, these chips are still$28-$35 at digi-key (in 24 qty)
[01:58:44] <jmkasunich> the FPGA?
[01:58:48] <SWPadnos> yep
[01:58:56] <jmkasunich> amazingly because they should be more, or less?
[01:59:21] <SWPadnos> well, there are faster ones for less, but these have the 5V I/O tolerance, which is getting rare
[01:59:31] <SWPadnos> newer fabric is less expensive per gate
[02:00:12] <jmkasunich> its crunching away on the "translate" step
[02:00:40] <SWPadnos> whatever that means (I don't know what the xilinx tools call the various stages - I've never run them directly :) )
[02:01:22] <SWPadnos> the spartan-3 (instead of spartan-2) is $20.80 in the same package, in singles
[02:01:35] <jmkasunich> but not 5V friendly?
[02:01:57] <SWPadnos> or $17.63 in 25 qty, so roughly 1/2 the price (and 4 ns instead of 5ns)
[02:02:02] <SWPadnos> I don't think so
[02:02:09] <SWPadnos> I think the datasheet says "3.3V tolerant" ;)
[02:02:24] <SWPadnos> the core is 1.2V
[02:03:54] <jmkasunich> it finished the translate and map phases, and is now doing place and route
[02:04:06] <jmkasunich> I think I should have specified the pinout first ;-/
[02:04:07] <SWPadnos> ok - I think that's the one that usually takes time
[02:04:10] <SWPadnos> heh
[02:04:16] <SWPadnos> helps in routing ...
[02:05:17] <jmkasunich> heh, probably easier to route without pin constraints
[02:05:33] <SWPadnos> "we're on a route to nowhere" ...
[02:07:38] <jmkasunich> placer time 2 mins 9 seconds
[02:07:59] <SWPadnos> without pin constraints? (or did it notice the pin file?)
[02:09:20] <jmkasunich> I'm sure its arbitrarily placing the I/Os
[02:09:36] <jmkasunich> probably shuffling them around to whatever gives the best internal routing
[02:10:01] <jmkasunich> place and route complete, 3 min 35 sec real, 1:19 cpu
[02:10:08] <SWPadnos> could be, but it wouldn't make a lot of sense
[02:10:26] <SWPadnos> unless it makes a nice compact blob that can then be "re-ported" later
[02:11:55] <jmkasunich> if you are doing a design that just barely fits in the device, you can place and route with no constraints to make its job easier, then design the PCB to suit
[02:12:05] <SWPadnos> I suppose so
[02:12:23] <jmkasunich> there is a schematic viewer of sorts
[02:12:36] <SWPadnos> though it's usually easier to let the FPGA config be determined by the board
[02:12:39] <SWPadnos> cool
[02:12:47] <SWPadnos> block diagram
[02:12:48] <SWPadnos> ?
[02:13:26] <jmkasunich> hard to tell
[02:13:40] <jmkasunich> I'm just clickin around with no idea what I'm doing
[02:14:04] <SWPadnos> there should be a modeling mode where you can make FPGA designs with schematic drawings
[02:14:17] <SWPadnos> I know the Altera tools have that (Quartus-II)
[02:14:32] <jmkasunich> looks like its kinda block diagram oriented
[02:15:41] <jmkasunich> definitely not user friendly tho
[02:15:51] <jmkasunich> no autogenerated schematic can be
[02:15:54] <SWPadnos> nope, and not portable either
[02:16:12] <jmkasunich> the whole point of a schematic is that it includes high level knowledge in the layout and flow of the components and signals
[02:16:21] <SWPadnos> you can take the VHDL code and stick it in an Altera FPGA if you want
[02:16:33] <SWPadnos> you can't take a Xilinx diagram and load it in the Altera package
[02:16:57] <jmkasunich> they have RTL and Technology schematics
[02:17:02] <jmkasunich> the RTL one might be portable
[02:17:12] <SWPadnos> runtime library?
[02:17:36] <jmkasunich> register transfer language?
[02:17:49] <jmkasunich> (guessing)
[02:17:52] <SWPadnos> xilinx is the company that has an option for compiling encrypted VHDL - as done with LabView
[02:18:23] <SWPadnos> LV would generate encrypted source code, and the xilinx tools compile it down to the FPGA. I coouldn't even look at the generated code
[02:18:32] <SWPadnos> which was exceedingly annoying
[02:18:33] <jmkasunich> scum
[02:18:45] <SWPadnos> indeed
[02:19:24] <SWPadnos> I suspect Altera and all the others do it too - IP has to be integrated with user code to be useful, and they wouldn't want you copying it now, would they?
[02:24:59] <jmkasunich> this tool has a very "busy" GUI - takes some getting used to
[02:25:51] <SWPadnos> yeah - like a lot of CAD-related software
[02:27:06] <jmkasunich> I found a pinout report, and as expected the pinout it came up bears no resemblence to the one we want
[02:27:25] <jmkasunich> I'm trying to figure out how to import the existing pin file
[02:27:57] <SWPadnos> is there a "target options" kind of menu item?
[02:29:08] <jmkasunich> user constraints
[02:29:17] <jmkasunich> with a subitem Assign Package Pins
[02:29:31] <SWPadnos> ah. I guess they call it a .pad file or something ...
[02:29:32] <jmkasunich> clicking that results in some disk thrashing, but nothing else that I can see
[02:30:11] <SWPadnos> you may have to re-synthesize (or re-generate output or whatever they call it) to get it to do anything
[02:30:24] <jmkasunich> the .PIN file in the emc source tree doesn't seem "right" for a machine read file
[02:30:34] <jmkasunich> there are what appear to be comments in it, with no delimiter of any kind
[02:30:39] <SWPadnos> no, it doesn't, but it has the information
[02:31:06] <jmkasunich> I was hoping to import that file, but I don't think thats how it works
[02:33:04] <SWPadnos> I'm trying to remember / recreate what I had to do to get the constraints into Altium
[02:35:46] <jmkasunich> something about this install is busted - when I click Help->Help Topics it thrashes a little, then nothing
[02:36:35] <SWPadnos> hmmm - are you still root?
[02:36:40] <jmkasunich> no
[02:36:50] <jmkasunich> installed as root, running as user
[02:36:58] <SWPadnos> I wonder if it matters (or if you have to install the docs in a separate step)
[02:45:30] <jepler> Help > Help Topics doesn't seem to work for me either
[02:45:59] <SWPadnos> I bet it expects to run Adobe reader, with a TOC kind of document
[02:53:14] <jepler> I imported the pluto servo code into the xilinx environment. It takes 5% of the FFs in the xc2s200 -- is that the right chip?
[02:53:27] <jmkasunich> yes
[02:53:44] <jmkasunich> 10K gates = 5% of 200K gates, sounds about right
[02:57:33] <jepler> max speed is not much different -- around 85MHz in ACEX, 93MHz in the xilinx.
[02:58:15] <jmkasunich> jepler: have you figured out how to enter pin constraints?
[02:58:45] <jepler> jmkasunich: not yet
[02:58:59] <jmkasunich> the tutorial told me to click on UserConstraints->AssignPackagePins, in the Processes box
[02:59:06] <jepler> but you got nothing
[02:59:08] <jmkasunich> when I did that pretty much nothing happened
[02:59:31] <jmkasunich> 'that was supposed to open the Pin Area Constraint Editor (pace)
[02:59:56] <jepler> did you get some kind of error in your terminal?
[02:59:59] <jmkasunich> there is an executable pace, I tried running that from the command line and got a libso warning
[03:00:00] <SWPadnos> I can dcc you the .ucf file petev sent me
[03:00:19] <jepler> NET "DIR<3>" LOC = "P33";
[03:00:29] <jepler> yeah I think you can manually insert lines like these in the .ucf file
[03:00:45] <jmkasunich> /home/jmkasunich/xilinx/bin/lin/_pace: error while loading shared libraries: libXm.so.3: cannot open shared object file: No such file or directory
[03:01:28] <jepler> jmkasunich: libmotif3: /usr/lib/libXm.so.3
[03:01:51] <jmkasunich> ?
[03:01:52] <jepler> "PACE" does come up for me
[03:02:04] <jepler> try installing that deb, but if I recall correctly I had to do another thing before it worked
[03:03:50] <jmkasunich> /home/jmkasunich/xilinx/bin/lin/_pace: error while loading shared libraries: libXm.so.3: cannot open shared object file: No such file or directory
[03:03:52] <jmkasunich> oops
[03:03:57] <jmkasunich> E: Couldn't find package libmotif3
[03:04:11] <jepler> Package: libmotif3
[03:04:12] <jepler> Priority: extra
[03:04:12] <jepler> Section: multiverse/libs
[03:04:16] <jepler> do you have multiverse enabled?
[03:04:23] <jmkasunich> * jmkasunich checks
[03:05:34] <jmkasunich> I do now ;-)
[03:05:39] <jmkasunich> installing libmotif3
[03:06:03] <SWPadnos> hmmm - I can't check in the ucf file from my windows machine
[03:06:42] <SWPadnos> I can dcc it to one or both of you, and one of you could check it in ...
[03:06:57] <jmkasunich> email it?
[03:07:00] <SWPadnos> ok
[03:07:27] <SWPadnos> there's information that you probably can't find easily, such as the I/O type for the PCI interface chip pins
[03:08:07] <jmkasunich> jepler: I got some kind of a registration code when I did the download
[03:08:11] <jmkasunich> but the install never asked for it
[03:08:26] <jmkasunich> when I start ISE it says registration UNKNOWN
[03:08:28] <jmkasunich> is yours the same?
[03:08:31] <jepler> me too
[03:09:53] <jepler> do you get a different error with libXm installed, when you try to start PACE?
[03:09:57] <SWPadnos> I've been told that the software is the same between the registered version and the free version, but there are some chip definition files missing (which prevents you from routing for high end or obsolete chips)
[03:10:04] <jepler> something about being unable to connect to the X server?
[03:10:10] <jmkasunich> when I try from the command line, I get:
[03:10:11] <jmkasunich> WARNING: en is not supported as a language. Using usenglish.
[03:10:11] <jmkasunich> Wind/U X-toolkit Error: wuDisplay: Can't open display
[03:10:29] <jepler> try: export DISPLAY=unix:0
[03:10:46] <SWPadnos> unix:0 - interesting
[03:10:53] <jmkasunich> also, when I tried from inside ise, I got:
[03:11:02] <jmkasunich> jmkasunich@ke-main-1006:~$ ps -A | grep pace
[03:11:02] <jmkasunich> 24241 pts/2 00:00:00 pace <defunct>
[03:11:23] <SWPadnos> ucf file on the way to both of you
[03:14:29] <jmkasunich> running pace from the command line (after the export).... it took a good 30 seconds to start up, but it did finally start
[03:14:36] <jepler> OK
[03:14:41] <jmkasunich> well, kind of
[03:15:04] <jmkasunich> there is a window, with File and Help in the menu bar, but it doesn't do anything
[03:15:11] <jmkasunich> still starting up maybe?
[03:15:33] <jepler> when I start it from within ise, it starts with the .ucf file for my project open
[03:15:41] <jepler> is file active? can you open a .ucf file?
[03:15:53] <SWPadnos> oh - I found a web page that says that you can't use a UCF file - you have to rename it to *.ucf (lower case) :/
[03:15:52] <jepler> I mean, is the File menu active
[03:15:57] <jmkasunich> no
[03:16:22] <jmkasunich> when I said "it doesn't do anything" I meant clicking on either File or Help does nada
[03:16:31] <jmkasunich> Its _still_ starting up - a toolbar just appeared
[03:16:59] <jmkasunich> wtf, is it written in interpreted basic being interpreted by java running under tcl?
[03:17:07] <SWPadnos> in a VM ;)
[03:17:28] <jepler> it's a svelte 80 megs here, and has only run for 30 CPU seconds even though I've been using it
[03:17:42] <SWPadnos> the first run may take longer - it may be creating some files for you, behind your back
[03:18:21] <jmkasunich> it doesn't even appear on top
[03:18:35] <jmkasunich> but Xorg does, 58% of the CPU
[03:19:09] <jmkasunich> ps -A | grep pace shows 4 seconds of CPU so far
[03:19:21] <SWPadnos> maybe it's pre-rendering every possible window configuration, so it's faster later
[03:19:24] <jmkasunich> actually the 4 seconds are for _pace
[03:21:03] <jmkasunich> something is messed up here
[03:21:08] <jmkasunich> I closed pace and ise
[03:21:17] <jmkasunich> the cpu is still pegged at 100%
[03:21:23] <jmkasunich> Xorg at 60%
[03:21:45] <jmkasunich> all I have running is IRC and some shells
[03:21:56] <jmkasunich> (the VMs are running, but the VM console is closed)
[03:22:10] <jepler> huh
[03:22:11] <jepler> wonder what's up
[03:22:11] <jmkasunich> I'm an idiot
[03:22:19] <jepler> you ... are ?
[03:22:23] <jmkasunich> I had a minimized firefox
[03:22:33] <jepler> i don't believe it
[03:22:36] <jmkasunich> every time I tried hitting help, it was openign a tab in firefox
[03:22:41] <SWPadnos> heh
[03:22:48] <jmkasunich> and every single one of those tabs is still loading something
[03:22:49] <SWPadnos> 17000 windows later ...
[03:22:56] <jmkasunich> no, only 4
[03:23:06] <jmkasunich> but all 4 are still loading
[03:23:23] <jmkasunich> even tho the file they're loading is from my local disk
[03:23:47] <jepler> SWPadnos: the ucf file arrived
[03:23:50] <SWPadnos> close 3 of them and see if the fourth speeds up ...
[03:23:51] <SWPadnos> cool
[03:24:07] <jmkasunich> closing those tabs dropped the CPU load
[03:24:10] <jepler> SWPadnos: is this file supposed to go with the other 5i20 files in the emc source tree?
[03:24:12] <jmkasunich> I closed them all
[03:24:34] <SWPadnos> I think so - pete V sent it to me when I first asked him about the FPGA source
[03:25:14] <SWPadnos> I don't know if he or Pete Wallace is the author (for license headers), but otherwise, it should be in there
[03:25:47] <SWPadnos> err - "should be in there" means "file should be in CVS" ...
[03:25:48] <jmkasunich> I'm guessing peter wallace
[03:26:01] <SWPadnos> it's likely
[03:26:39] <jmkasunich> ok, pace opens from ISE now
[03:26:40] <jmkasunich> yay!
[03:26:52] <jmkasunich> its still got "issues", very very inefficient X
[03:30:41] <SWPadnos> cradek, heh - I'm surprised you answered that query :)
[03:30:49] <jepler> ERROR:NgdBuild:756 - Line 628 in 'hostmot5.ucf': Could not find net(s) 'pwm<8>'
[03:30:51] <jepler> in the design. To suppress this error specify the correct net name or remove
[03:30:54] <jepler> the constraint.
[03:30:55] <cradek> guess he had left already anyway
[03:31:03] <SWPadnos> yep
[03:31:08] <jepler> trying to use this ucf file with the vhdl in the source tree gives a bunch of errors
[03:31:21] <SWPadnos> I wonder if that was for the 8-axis version
[03:31:39] <SWPadnos> PWM<8> could imply something like that
[03:33:07] <jepler> how many PWM are there supposed to be?
[03:33:50] <jmkasunich> SWPadnos: looks like 12 channels actually
[03:33:59] <SWPadnos> hmmm - that's not it. the PWMx are numbered 0-7, not 1-8
[03:33:59] <jepler> hostmot5-4e.vhd:PWM: inout STD_LOGIC_VECTOR (3 downto 0);
[03:34:15] <jepler> the first error is about PWM<4>
[03:34:37] <SWPadnos> sorry - I'm not sure what hostmot that's supposed to be for then. the 8-axis one I have only goes up to 7
[03:34:58] <jepler> the ucf file has entries up to 11
[03:35:19] <jmkasunich> the ucf file almost looks like a concatenation of a couple
[03:35:59] <SWPadnos> yeah - almost
[03:35:59] <jmkasunich> it starts with ads, int, b1, a1, b0, a1, blah blah, for channels 0-3
[03:36:39] <SWPadnos> here's the message PeteV sent the file with:
[03:36:41] <SWPadnos> "See attached. You may need to make some modifications.
[03:36:43] <jmkasunich> never mind, I'm not sure what I'm seeing
[03:36:44] <SWPadnos>
[03:36:44] <SWPadnos> ~petev"
[03:36:46] <SWPadnos> I guess he'w right :)
[03:36:48] <SWPadnos> he's
[03:38:46] <jmkasunich> "cat Hostmot5_4.ucf | grep -v "#" | grep LOC" will filter a lot of crap and let you see what is going on
[03:38:53] <jmkasunich> the pins don't match the design we are using
[03:39:10] <jmkasunich> this pinout is for 12 encoders and 12 pwms
[03:39:39] <SWPadnos> ok- I guess I should have said I'd send you "a" ucf file :)
[03:39:52] <jmkasunich> 119 total pins (72 I/O, the rest are for the PCI interface and clocks and such)
[03:39:59] <SWPadnos> the chip pins do correspond to header pins though
[03:41:10] <jepler> having removed the lines for each of those 4..11 items, it's reached Place & Route
[03:41:40] <jepler> 24% FFs used, 34% LUTs used
[03:41:51] <jmkasunich> yeah, amazing isn't it
[03:42:13] <jmkasunich> I'm definitely getting two of them
[03:42:20] <jmkasunich> one for my machine, one to play with
[03:42:37] <SWPadnos> heh
[03:42:49] <SWPadnos> the generic I/O won't be connected though
[03:43:07] <jmkasunich> you mean with jeff's edited .ucf
[03:43:18] <jmkasunich> sure it will, just not where you expect it ;-)
[03:43:36] <SWPadnos> I don't see an example of what the IOBITSA or IOBITSB are named
[03:43:40] <SWPadnos> right :)
[03:43:55] <SWPadnos> they may be, oddly enough, IOBITSA<n> :)
[03:44:12] <jmkasunich> after we've got our boards and can test, we should prepare a proper project file, with ucf and all the rest, test it, and commit it - and make the driver use that bitfile, not the mesa one
[03:44:22] <jepler> yes yes a thousand times yes
[03:44:31] <jmkasunich> that way it is reproducable from the source
[03:44:42] <jepler> and figure out how to use the commandline version of the ise programs
[03:45:05] <jmkasunich> when running the GUI, it logs the command lines that it invokes
[03:45:09] <jepler> yep I've seen that
[03:45:27] <jmkasunich> cmd line is covered in one of hte manuals too
[03:45:58] <SWPadnos> I think you can make the equivalent of a makefile for the cmd line tools
[03:46:41] <jepler> "Logical Network CS0 has no load"
[03:46:47] <jepler> so many warnings, and i know what none of them mean
[03:47:09] <jmkasunich> so much to learn
[03:47:20] <SWPadnos> so very little time
[03:48:23] <jepler> at least jmkasunich seems to be committed to writing the stepping firmware, I was worried it would fall to me
[03:48:43] <jmkasunich> the thing that scares me is the setup and hold time crap
[03:49:40] <jmkasunich> the DDS part is easier in hardware than in software, IMO
[03:49:51] <jmkasunich> then theres this box called setup and hold
[03:49:57] <jmkasunich> output of that is step/dir
[03:50:05] <jmkasunich> a step/dir to quadrature converter is easy
[03:50:23] <jmkasunich> and that quadrature can be routed to a normal encoder counter block
[03:50:51] <SWPadnos> you output a clock from the DDS block, and it can drive any number of sequencers - step/dir, quad, 5-phase ...
[03:51:00] <jmkasunich> yep
[03:51:01] <SWPadnos> table lookups are relatively inexpensive
[03:51:16] <jmkasunich> the problem is that setup/hold might ignore some clock pulses
[03:51:27] <jmkasunich> so you need to count the actual pulses for feedback
[03:51:33] <SWPadnos> but then setup/hold need to be able to pause the DDS clock generator
[03:51:57] <jmkasunich> hmm, thats a thought
[03:52:23] <SWPadnos> it makes for a discontinuity at 0, but there is one anyeay in the machine (stiction, etc)
[03:52:42] <SWPadnos> and there has to be one for the stepgen, since that's the timing spec ;)
[03:52:54] <jepler> it didn't meet the timing constraints
[03:53:04] <jepler> Constraint | Requested | Actual | Logic | Absolute |Number of
[03:53:07] <jepler> | | | Levels | Slack |errors
[03:53:11] <jepler> ------------------------------------------------------------------------------------------------------
[03:53:15] <jepler> * OFFSET = OUT 22 ns AFTER COMP "LCLK" | 22.000ns | 26.514ns | 8 | -4.514ns | 32
[03:53:38] <jmkasunich> so: if sign(addval) != sign(oldaddval) { pause for hold time ; toggle dir ; pause for setup time ; resume dds using new addval }
[03:53:56] <jepler> 'night guys
[03:54:02] <SWPadnos> something like that
[03:54:05] <SWPadnos> night jepler
[03:54:05] <jmkasunich> jepler: what that last post mean to us mortals?
[03:54:27] <jmkasunich> one timing constraint not met?
[03:54:49] <SWPadnos> it means that the OUT signal(s) doesn't meet the specified timing target of 22ns, the actual timing is 26.514ns, which is 4.514ns too slow
[03:54:56] <SWPadnos> and there are 32 errors of that type
[03:54:56] <jepler> what SWPadnos said
[03:55:17] <SWPadnos> jepler, did you specify all the IO pins?
[03:55:29] <jmkasunich> so for that particular place/route, you need to either slow the clock, or try again
[03:55:35] <jepler> SWPadnos: no, I deleted the lines that didn't apply and left the rest unspecified
[03:55:50] <SWPadnos> ok - that may be a problem
[03:55:59] <SWPadnos> I don't know enough about it to fix it yet though
[03:56:14] <jepler> it suggests some things I can try doing
[03:56:19] <jepler> but that's for another day
[03:56:29] <jmkasunich> goodnight jeff
[03:56:31] <SWPadnos> you can tell it that a slower clock is acceptable, in which case the (more lax) timing will be met
[03:56:50] <SWPadnos> or you can tell it to optimize more (which it probably can't do without fully constrained I/O)
[03:58:32] <SWPadnos> there should be some "super-optimization" mode, where it'll basically run until you tell it to stop
[03:59:13] <SWPadnos> I recall that Atmel had some IP that they claimed was faster than most companies could make, because they ran the optimizer on basically all the PCs in the company over a weekend
[04:09:15] <SWPadnos> ok - I'm not sure if peteve generated the bitfile in CVS< but I've asked him for the complete set of files used to generate it (or to tell me that I should ask Pete W)
[04:09:50] <jmkasunich> sounds good
[04:13:20] <SWPadnos> well, strangely enough, it may be bedtime for me
[04:13:22] <SWPadnos> good night
[04:21:48] <jmkasunich> goodnight
[04:48:07] <jmkasunich> hmm... I commented out the constraints on channels 4-11 (just like jepler did) and I got a place-route that met all constraints
[05:43:39] <SWPadnos> jmkasunich, you may have chosen a different speed grade than Jeff did. the actual part is the -5 speed grade (normal, vs -6 which is high performance)
[05:43:53] <jmkasunich> I did pick the 6
[05:44:02] <jmkasunich> I thought you were sleeping ;-)
[05:44:19] <SWPadnos> I was going to, but got co-opted by the cat, and got un-tired :)
[05:44:51] <SWPadnos> he was avtually drinking quite abit, but only if I'd watch and pet him from time to time
[05:44:53] <SWPadnos> actually
[05:46:41] <SWPadnos> oh, and petev emailed me back - he didn't generate any bitfiles, he wrote the utility that converts the bitfile to a C header, and may have done the driver (though he didn't take credit for that)
[05:46:51] <SWPadnos> so I'll ask Pete W tomorrow
[05:48:14] <jmkasunich> ok
[05:56:48] <SWPadnos> ok - I just sent off a message to Pete W, asking for files and mentioning that several of the active developers will be buying 5i20 cards in the next couple of weeks
[05:56:59] <jmkasunich> cool
[05:57:11] <jmkasunich> we're looking at well over $1000 aren't we
[05:57:19] <SWPadnos> closer to $2000
[05:57:33] <SWPadnos> a little over, I think
[05:58:41] <SWPadnos> one thing that may make the group buy a little less interesting is warrantee issues
[05:58:56] <jmkasunich> hmmm
[05:59:03] <jmkasunich> didn't think about that
[05:59:05] <SWPadnos> I'd rather not be listed as the owner of all that stuff - if anything goes wrong, people should be able to return the things directly
[05:59:16] <SWPadnos> it's on my list for the phone call
[06:03:10] <jmkasunich> ok, bedtime for me
[06:03:17] <SWPadnos> ok - good night :)
[13:23:34] <jepler> good morning
[13:23:44] <jepler> is it a -5 or a -6 chip?
[13:23:51] <jepler> yes, I'd chosen -5
[20:07:40] <SWPadnos> woohoo! Peter Wallace just sent me the code (both 4 and 8 axis versions), and he's also offered the qty. 25 pricing for our group buy
[20:08:34] <cradek> wow
[20:08:52] <SWPadnos> yeah - that's another ~10% off :)
[20:09:11] <SWPadnos> I'm about to forward the code - would you like a copy as well?
[20:09:28] <cradek> why not put it in cvs?
[20:09:56] <SWPadnos> because I'm on a Windows machine and tortoise CVS doesn't seem to work over SSH ...
[20:10:05] <SWPadnos> at least, it hasn't yet
[20:10:34] <cradek> thanks, but I can just wait until someone checks it in then
[20:10:38] <SWPadnos> ok
[20:11:14] <jepler> I'll take a copy if you want to send it to me
[20:11:19] <SWPadnos> sent.
[20:11:46] <SWPadnos> he had a note or two on the project files as well (he uses ISE 6.xx)
[20:12:00] <jepler> I don't know what version I have
[20:12:03] <jepler> the latest, I assume
[20:12:09] <SWPadnos> 8.something, I bet
[20:12:58] <cradek> what's the 4 axis H bridge card they talk about?
[20:13:19] <SWPadnos> you mean the 7I30?
[20:13:48] <cradek> aha, couldn't spot it for some reason
[20:13:47] <SWPadnos> it takes external power and connects directly to the PWM/DIR outputs of the card
[20:14:48] <SWPadnos> well, with qty. 25 pricing, getting some BLCD and other servo drives for fun is more palatable
[20:14:53] <SWPadnos> err - BLDC
[20:15:33] <SWPadnos> I guess I'll send an email only to the developers list - that should keep Peter happy
[20:19:31] <cradek> the 7I30 looks nice and affordable
[20:19:52] <SWPadnos> $64 at the special price
[20:20:10] <SWPadnos> oops - $65
[20:21:02] <SWPadnos> at that price, the 4-axis analog interface card plus the 5I20 is less than $200
[20:21:17] <cradek> yeah I was thinking that....
[20:21:18] <SWPadnos> and the 4-axis H-bridge plus 5I20 is $210
[20:21:21] <cradek> what's my deadline to decide?
[20:21:43] <SWPadnos> we were thinking of cutting it off on the 20th or so
[20:21:53] <cradek> ok, cool
[20:22:02] <SWPadnos> the sales person thought it would be good to place the order by the 22nd
[20:22:17] <skunkworks> very nice.
[20:22:55] <SWPadnos> also, they don't have a huge stock of some things, and they're willing to drop-ship (and bill directly), so some people can opt to be on the "low priority" list, which means you won't be charged ultil later, when your stuff ships
[20:36:25] <A-L-P-H-A> I don't think they'll mark my stuff as 'gift' so I think I'll do it through you please.
[20:36:57] <SWPadnos> they also won't charge you the 2.9% premium for PayPal, or double shipping fees ...
[20:37:15] <SWPadnos> (remember - there's a share of the inbound shipping to pay, plus shipping to you)
[20:37:23] <A-L-P-H-A> heh... can you beat $25 brokerage fess + taxes?
[20:37:26] <SWPadnos> with the discounted prices, they won't ship for free ;)
[20:37:39] <SWPadnos> hmmm - probably
[20:37:45] <A-L-P-H-A> see. :)
[20:37:59] <SWPadnos> though you may still have to pay the fees, if the customs person has a stick up their ass that day
[20:38:31] <A-L-P-H-A> doubtful, if you ship via USPS. That brokerage fee is usually $10.
[20:39:15] <A-L-P-H-A> I've had brokerage fees from UPS (brown), that totalled $56 for an box. I was pissed... as the router inside was only worth $36.
[20:39:23] <A-L-P-H-A> I complained like mad, and they waived it.
[20:39:29] <SWPadnos> ok - wither way is fine with me. I'm not sure they'll want to do drop shipments anyway, with the lower pricing (I've been communicating with two different people there)
[20:39:47] <SWPadnos> s/wither/either/
[20:39:51] <A-L-P-H-A> I gathered.
[20:40:21] <A-L-P-H-A> SWPadnos: if you need my email it's ll@lloydleung.com
[20:40:27] <SWPadnos> ok
[20:40:30] <SWPadnos> thanks
[20:40:45] <A-L-P-H-A> actually, you should have already had that. :)
[20:40:54] <A-L-P-H-A> we've sent email before between each other.
[20:41:03] <SWPadnos> I think so
[20:41:06] <A-L-P-H-A> anyways... what's yours so I can whitelist it?
[20:41:49] <SWPadnos> actually, I'm not sure we have - I posted the AVR code on one of my websites
[20:41:54] <SWPadnos> spadnos@sover.net
[20:48:56] <SWPadnos> could people look at the email I'm composing and give any suggestions: http://pastebin.ca/275815
[20:49:07] <SWPadnos> well, minus the line numbers
[20:50:12] <A-L-P-H-A> checking
[20:50:49] <SWPadnos> one revision already: http://pastebin.ca/275818
[20:51:38] <A-L-P-H-A> you sure are wordy.
[20:51:44] <SWPadnos> yes
[20:52:23] <A-L-P-H-A> "Updated pricing will be up later today, as well as more details as they become available." That's like half your sentence.
[20:53:14] <A-L-P-H-A> you should also give when responses to purchase are due.
[20:53:17] <SWPadnos> well, I wanted to say "late today" because jmk is travelling
[20:53:24] <SWPadnos> that's in the second revision
[20:53:42] <SWPadnos> not "later today" ...
[20:54:11] <A-L-P-H-A> okay. "late tonight (EST)"
[20:54:18] <SWPadnos> heh
[20:54:25] <SWPadnos> I'm not sure what time zone he's in :)
[20:54:49] <A-L-P-H-A> I believe he's CST.
[20:55:06] <A-L-P-H-A> ooooooooooooh wait... that was cradek and jepler.
[20:55:07] <SWPadnos> he is when he's not on the road ...
[20:55:12] <A-L-P-H-A> don't know where is jmkasunich.
[20:55:19] <cradek> jmk is eastern
[20:55:22] <SWPadnos> he's from Cleveland, so EST, but he's not there
[20:55:41] <A-L-P-H-A> if there's no solid information, why relay it?
[20:56:01] <A-L-P-H-A> Please check that page regularly, to view any updates.
[20:56:06] <SWPadnos> there is some solid information, and there will be more later. let's not dewll on how I worded the fact that the page will be updated
[20:56:13] <SWPadnos> dwell
[20:56:28] <SWPadnos> is there more information you think should be included?
[20:56:36] <A-L-P-H-A> Hello Everyone.
[20:56:43] <SWPadnos> maybe a direct link to Mesa would be good
[20:56:45] <A-L-P-H-A> Hello All, is kinda texan... low class.
[20:57:01] <cradek> yeah, I prefer "Hi all"
[20:57:26] <A-L-P-H-A> well... you can be GWB's little bro. go and enjoy, Jebby
[20:57:29] <SWPadnos> not "yo dudes and dudettes"
[20:57:42] <SWPadnos> that's hi y'all ;)
[20:57:50] <A-L-P-H-A> doubtful that there are many dudettes in the list.
[20:58:07] <A-L-P-H-A> if there are, less than a handful.
[20:58:34] <SWPadnos> but they're a handfull
[20:58:37] <SWPadnos> oops
[20:59:10] <A-L-P-H-A> argh................ did you ever hear about the man that got breast implants for a $100K bet?
[20:59:32] <A-L-P-H-A> I saw the last night on digg.com it messed me up.
[20:59:53] <SWPadnos> no. thank you
[21:00:03] <jepler> you mean "no. thank god."
[21:01:03] <SWPadnos> well, I'm a non-believer ;)
[21:01:49] <skunkworks> 'no. thank the big bang'
[21:05:30] <SWPadnos> ok - how about this? http://pastebin.ca/275854
[21:07:05] <cradek> does pete w want you to advertise this and maybe get a bunch of orders?
[21:07:33] <SWPadnos> he said he prefers to extend the offer to developers, but if some users order, they won't really care
[21:07:48] <SWPadnos> I think emailing to the devel list only is a good middle-ground
[21:08:22] <cradek> I was just wondering, because it sounds like he's short on cards (and I think all the active developers already know about the offer)
[21:08:50] <SWPadnos> well, that's true
[21:09:00] <cradek> just a thought - you know the situation better than I do
[21:09:25] <SWPadnos> I'm not sure it has to be "people who regularly write code" - Ray should have one if he doesn't already, since he tends to do a lot of testing (and I'm not sure he knows about it)
[21:09:59] <cradek> ok I see
[21:10:22] <SWPadnos> I did point out that I was considering emailing to both lists, and he didn't ask me not to
[21:10:25] <cradek> (there are 211 subscribers to -devel)
[21:10:53] <SWPadnos> heh - another factor of 4 or so over the developer list at SF, which is 4-8x the number of active develpers ;)
[21:11:34] <cradek> yeah, lots of people are interested in the ongoing development even if they don't usually contribute
[21:11:35] <SWPadnos> I wonder if JonE would want one ;)
[21:16:09] <skunkworks> I think I am an interested party ;)
[21:16:26] <SWPadnos> apparently
[21:16:36] <skunkworks> cradek: have you played with your pluto yet?
[21:16:43] <SWPadnos> cradek, how many people are subscribed to hte users list?
[21:27:18] <cradek> skunkworks: not yet... seemed like I was busy all weekend
[21:27:23] <cradek> SWPadnos: 630
[21:27:36] <SWPadnos> ok, so the devel list is a significantly smaller crowd
[21:27:48] <skunkworks> cradek: same here. have not gotten back to the breakout board.
[21:27:54] <SWPadnos> but you have a point that it's significantly larger than the number of developers