Mesa HostMot2

loadrt hostmot2

 loadrt hm2_pci config="firmware=hm2/5i20/SVST8_4.BIT num_encoders=3
num_pwmgens=3 num_stepgens=1"

 (bit i/o) True if the watchdog has bit, False if the watchdog has not
bit. If the watchdog has bit and the has_bit bit is True, the user can
reset it to False to resume operation.

 (u32 read/write) Watchdog timeout, in nanoseconds. This is initialized
to 1,000,000,000 (1 second) at module load time. If more than this
amount of time passes between calls to the pet_watchdog() function, the
watchdog will bite.

dmesg > hm2.txt

sudo dmesg -c

[HOSTMOT2] +
DRIVER=hm2_pci +
BOARD=5i20 +
 CONFIG="firmware=hm2/5i20/SVST8_4.BIT num_encoders=1 num_pwmgens=1
num_stepgens=3"

The above configuration produced this printout .

[ 1141.053386] hm2/hm2_5i20.0: 72 I/O Pins used: +
[ 1141.053394] hm2/hm2_5i20.0: IO Pin 000 (P2-01): IOPort +
[ 1141.053397] hm2/hm2_5i20.0: IO Pin 001 (P2-03): IOPort +
 [ 1141.053401] hm2/hm2_5i20.0: IO Pin 002 (P2-05): Encoder #0, pin B
(Input) +
 [ 1141.053405] hm2/hm2_5i20.0: IO Pin 003 (P2-07): Encoder #0, pin A
(Input) +
[ 1141.053408] hm2/hm2_5i20.0: IO Pin 004 (P2-09): IOPort +
 [ 1141.053411] hm2/hm2_5i20.0: IO Pin 005 (P2-11): Encoder #0, pin
Index (Input) +
[ 1141.053415] hm2/hm2_5i20.0: IO Pin 006 (P2-13): IOPort +
 [ 1141.053418] hm2/hm2_5i20.0: IO Pin 007 (P2-15): PWMGen #0, pin Out0
(PWM or Up) (Output) +
[ 1141.053422] hm2/hm2_5i20.0: IO Pin 008 (P2-17): IOPort +
 [ 1141.053425] hm2/hm2_5i20.0: IO Pin 009 (P2-19): PWMGen #0, pin Out1
(Dir or Down) (Output) +
[ 1141.053429] hm2/hm2_5i20.0: IO Pin 010 (P2-21): IOPort +
 [ 1141.053432] hm2/hm2_5i20.0: IO Pin 011 (P2-23): PWMGen #0, pin
Not-Enable (Output) +
<snip>... +
 [ 1141.053589] hm2/hm2_5i20.0: IO Pin 060 (P4-25): StepGen #2, pin
Step (Output) +
 [ 1141.053593] hm2/hm2_5i20.0: IO Pin 061 (P4-27): StepGen #2, pin
Direction (Output) +
 [ 1141.053597] hm2/hm2_5i20.0: IO Pin 062 (P4-29): StepGen #2, pin
(unused) (Output) +
 [ 1141.053601] hm2/hm2_5i20.0: IO Pin 063 (P4-31): StepGen #2, pin
(unused) (Output) +
 [ 1141.053605] hm2/hm2_5i20.0: IO Pin 064 (P4-33): StepGen #2, pin
(unused) (Output) +
 [ 1141.053609] hm2/hm2_5i20.0: IO Pin 065 (P4-35): StepGen #2, pin
(unused) (Output) +
[ 1141.053613] hm2/hm2_5i20.0: IO Pin 066 (P4-37): IOPort +
[ 1141.053616] hm2/hm2_5i20.0: IO Pin 067 (P4-39): IOPort +
[ 1141.053619] hm2/hm2_5i20.0: IO Pin 068 (P4-41): IOPort +
[ 1141.053621] hm2/hm2_5i20.0: IO Pin 069 (P4-43): IOPort +
[ 1141.053624] hm2/hm2_5i20.0: IO Pin 070 (P4-45): IOPort +
[ 1141.053627] hm2/hm2_5i20.0: IO Pin 071 (P4-47): IOPort +
[ 1141.053811] hm2/hm2_5i20.0: registered +
[ 1141.053815] hm2_5i20.0: initialized AnyIO board at 0000:02:02.0

/usr/share/doc/hostmot2-firmware-mesa-<board>-hostmot2

 (Bit, Out) Normal state of the hardware input pin. Both full GPIO pins
and IO pins used as inputs by active module instances have this pin.

 (Bit, Out) Inverted state of the hardware input pin. Both full GPIO
pins and IO pins used as inputs by active module instances have this
pin.

 (Bit, In) Value to be written (possibly inverted) to the hardware
output pin. Only full GPIO pins have this pin.

 (Bit, RW) This parameter only has an effect if the "is_output"
parameter is true. If this parameter is true, the output value of the
GPIO will be the inverse of the value on the "out" HAL pin. Only full
GPIO pins and IO pins used as outputs by active module instances have
this parameter. To invert an active module pin you have to invert the
GPIO pin not the module pin.

 (Bit, RW) This parameter only has an effect if the "is_output"
parameter is true. If this parameter is false, the GPIO behaves as a
normal output pin: the IO pin on the connector is driven to the value
specified by the "out" HAL pin (possibly inverted), and the value of
the "in" and "in_not" HAL pins is undefined. If this parameter is true,
the GPIO behaves as an open-drain pin. Writing 0 to the "out" HAL pin
drives the IO pin low, writing 1 to the "out" HAL pin puts the IO pin
in a high-impedance state. In this high-impedance state the IO pin
floats (weakly pulled high), and other devices can drive the value; the
resulting value on the IO pin is available on the "in" and "in_not"
pins. Only full GPIO pins and IO pins used as outputs by active module
instances have this parameter.

 (Bit, RW) If set to 0, the GPIO is an input. The IO pin is put in a
high-impedance state (weakly pulled high), to be driven by other
devices. The logic value on the IO pin is available in the "in" and
"in_not" HAL pins. Writes to the "out" HAL pin have no effect. If this
parameter is set to 1, the GPIO is an output; its behavior then depends
on the "is_opendrain" parameter. Only full GPIO pins have this
parameter.

 (Bit, In) Switches between position control mode (0) and velocity
control mode (1). Defaults to position control (0).

(s32, Out) Feedback position in counts (number of steps).

(Bit, In) Enables output steps. When false, no steps are generated.

 (Float, In) Target position of stepper motion, in user-defined
position units.

 (Float, Out) Feedback position in user-defined position units (counts
/ position_scale).

 (Float, In) Target velocity of stepper motion, in user-defined
position units per second. This pin is only used when the stepgen is in
velocity control mode (control-type=1).

 (Float, Out) Feedback velocity in user-defined position units per
second.

 (u32, RW) Minimum duration of stable Direction signal after a step
ends, in nanoseconds.

 (u32, RW) Minimum duration of stable Direction signal before a step
begins, in nanoseconds.

 (Float, RW) Maximum acceleration, in position units per second per
second. If set to 0, the driver will not limit its acceleration.

 (Float, RW) Maximum speed, in position units per second. If set to 0,
the driver will choose the maximum velocity based on the values of
steplen and stepspace (at the time that maxvel was set to 0).

 (Float, RW) Converts from counts to position units. position = counts
/ position_scale

 (u32, RW) Output format, like the step_type modparam to the software
stegen(9) component. 0 = Step/Dir, 1 = Up/Down, 2 = Quadrature. In
Quadrature mode (step_type=2), the stepgen outputs one complete Gray
cycle (00 -> 01 -> 11 -> 10 -> 00) for each "step" it takes.

(u32, RW) Duration of the step signal, in nanoseconds.

(u32, RW) Minimum interval between step signals, in nanoseconds.

 (Bit, RW) This parameter only has an effect if the "is_output"
parameter is true. If this parameter is true, the output value of the
GPIO will be the inverse of the value on the "out" HAL pin.

 (Bit, RW) If this parameter is false, the GPIO behaves as a normal
output pin: the IO pin on the connector is driven to the value
specified by the "out" HAL pin (possibly inverted). If this parameter
is true, the GPIO behaves as an open-drain pin. Writing 0 to the "out"
HAL pin drives the IO pin low, writing 1 to the "out" HAL pin puts the
IO pin in a high-impedance state. In this high-impedance state the IO
pin floats (weakly pulled high), and other devices can drive the value;
the resulting value on the IO pin is available on the "in" and "in_not"
pins. Only full GPIO pins and IO pins used as outputs by active module
instances have this parameter.

 (Bit, In) If true, the pwmgen will set its Not-Enable pin false and
output its pulses. If "enable" is false, pwmgen will set its Not-Enable
pin true and not output any signals.

(Float, In) The current pwmgen command value, in arbitrary units.

 (s32, RW) This emulates the output_type load-time argument to the
software pwmgen component. This parameter may be changed at runtime,
but most of the time you probably want to set it at startup and then
leave it alone. Accepted values are 1 (PWM on Out0 and Direction on
Out1), 2 (Up on Out0 and Down on Out1), 3 (PDM mode, PDM on Out0 and
Dir on Out1), and 4 (Direction on Out0 and PWM on Out1, "for locked
antiphase").

 (Float, RW) Scaling factor to convert "value" from arbitrary units to
duty cycle: dc = value / scale. Duty cycle has an effective range of
-1.0 to +1.0 inclusive, anything outside that range gets clipped.

 (u32, RW) This specifies the PDM frequency, in Hz, of all the pwmgen
instances running in PDM mode (mode 3). This is the "pulse slot
frequency"; the frequency at which the pdm generator in the AnyIO board
chooses whether to emit a pulse or a space. Each pulse (and space) in
the PDM pulse train has a duration of 1/pdm_frequency seconds. For
example, setting the pdm_frequency to 2e6 (2 MHz) and the duty cycle to
50% results in a 1 MHz square wave, identical to a 1 MHz PWM signal
with 50% duty cycle. The effective range of this parameter is from
about 1525 Hz up to just under 100 MHz. Note that the max frequency is
determined by the ClockHigh frequency of the Anything IO board; the
5i20 and 7i43 both have a 100 MHz clock, resulting in a 100 Mhz max PDM
frequency. Other boards may have different clocks, resulting in
different max PDM frequencies. If the user attempts to set the
frequency too high, it will be clipped to the max supported frequency
of the board.

 (u32, RW) This specifies the PWM frequency, in Hz, of all the pwmgen
instances running in the PWM modes (modes 1 and 2). This is the
frequency of the variable-duty-cycle wave. Its effective range is from
1 Hz up to 193 KHz. Note that the max frequency is determined by the
ClockHigh frequency of the Anything IO board; the 5i20 and 7i43 both
have a 100 MHz clock, resulting in a 193 KHz max PWM frequency. Other
boards may have different clocks, resulting in different max PWM
frequencies. If the user attempts to set the frequency too high, it
will be clipped to the max supported frequency of the board.
Frequencies below about 5 Hz are not terribly accurate, but above 5 Hz
they're pretty close.

 (Bit, RW) This parameter only has an effect if the "is_output"
parameter is true. If this parameter is true, the output value of the
GPIO will be the inverse of the value on the "out" HAL pin.

 (Bit, RW) If this parameter is false, the GPIO behaves as a normal
output pin: the IO pin on the connector is driven to the value
specified by the "out" HAL pin (possibly inverted). If this parameter
is true, the GPIO behaves as an open-drain pin. Writing 0 to the "out"
HAL pin drives the IO pin low, writing 1 to the "out" HAL pin puts the
IO pin in a high-impedance state. In this high-impedance state the IO
pin floats (weakly pulled high), and other devices can drive the value;
the resulting value on the IO pin is available on the "in" and "in_not"
pins. Only full GPIO pins and IO pins used as outputs by active module
instances have this parameter.

(s32, Out) Number of encoder counts since the previous reset.

 (Bit, I/O) When this pin is set to True, the count (and therefore also
position) are reset to zero on the next Index (Phase-Z) pulse. At the
same time, index-enable is reset to zero to indicate that the pulse has
occurred.

(Float, Out) Encoder position in position units (count / scale).

 (s32, Out) Total number of encoder counts since the start, not
adjusted for index or reset.

 (Bit, In) When this pin is TRUE, the count and position pins are set
to 0. (The value of the velocity pin is not affected by this.) The
driver does not reset this pin to FALSE after resetting the count to 0,
that is the user's job.

(Float, Out) Estimated encoder velocity in position units per second.

 (Bit, RW) Set to False (the default) for Quadrature. Set to True for
Up/Down or for single input on Phase A. Can be used for a frequency to
velocity converter with a single input on Phase A when set to true.

 (Bit, RW) If set to True (the default), the quadrature counter needs
15 clocks to register a change on any of the three input lines (any
pulse shorter than this is rejected as noise). If set to False, the
quadrature counter needs only 3 clocks to register a change. The
encoder sample clock runs at 33 MHz on the PCI AnyIO cards and 50 MHz
on the 7i43.

 (Bit, RW) If set to True, the rising edge of the Index input pin
triggers the Index event (if index-enable is True). If set to False,
the falling edge triggers.

 (Bit, RW) If set to True, the Index input pin only has an effect if
the Index-Mask input pin is True (or False, depending on the
index-mask-invert pin below).

 (Bit, RW) If set to True, Index-Mask must be False for Index to have
an effect. If set to False, the Index-Mask pin must be True.

 (Float, RW) Converts from "count" units to "position" units. A
quadrature encoder will normally have 4 counts per pulse so a 100 PPR
encoder would be 400 counts per revolution. In ".counter-mode" a 100
PPR encoder would have 100 counts per revelution as it only uses the
rising edge of A and direction is B.

 (Float, RW) When the encoder is moving slower than one pulse for each
time that the driver reads the count from the FPGA (in the hm2_read()
function), the velocity is harder to estimate. The driver can wait
several iterations for the next pulse to arrive, all the while
reporting the upper bound of the encoder velocity, which can be
accurately guessed. This parameter specifies how long to wait for the
next pulse, before reporting the encoder stopped. This parameter is in
seconds.